8-bit 50MS/s ADC architecture choice

[neoflash]

Hi,

The requirement is to have 50MS/s data throughput. I have two choices:

1. pipelined ADC
2. 8-way interleaved SAR

The technology will be on 0.18um. Which topology will be more efficient in power/area?

Regards,
Neo

 

[Dominik Przyborowski]

SAR with capacitive DAC should give you the lowest power (with appropriate switching scheme).
In classic pipeline you have to design fast opamp with very high gain which need quite lot current (even You choose hi-performance topologies like DRFC or IDRFC). The second option is pipeline with charge transfer amplifiers but it still more power consuming than SAR.

 

[neoflash]

SAR with capacitive DAC should give you the lowest power (with appropriate switching scheme).
In classic pipeline you have to design fast opamp with very high gain which need quite lot current (even You choose hi-performance topologies like DRFC or IDRFC). The second option is pipeline with charge transfer amplifiers but it still more power consuming than SAR.

I agree SAR can very efficient in low speed mode. 8x interleaving is slightly concerning me. Do you think that with 8x interleaving, SAR still have a lot advantage in power?

 

[Dominik Przyborowski]

You need to check in recent publications. In my team guys designed in 0.13um 8channels 10bit SAR working with 50MS/s and consuming ~3uW/ch·bit·MS/s. In 32nm (if I good remember) guys from Leuven designed 8bits sar working with 3GS/s and consuming <1mW total power for highest sampling rate.
I'm not sure about interleaving influence for power consumption.

In classic pipeline You need opamp with around 110dB of open loop gain and GBW around 1GHz so it takes more static current than whole SAR ADC in dynamic operation.