8 8 register_alu need help urgent

[mar mar lwin]

register_alu

The task is to design a component which could be used in the core of a microprocessor:

We shall call this Register_ALU:
• the design will contain 8 8-bit registers which can be loaded from an external input;
• the design will contain a block of logic which will have two 8-bit inputs A[7..0] and B[7..0], and will produce one 8-bit output C[7..0];
• the output will be formed as
o A and B, or
o A or B, or
o A plus B, or
o A minus B;
• the operation {logical and, logical or, arithmetic plus, arithmetic minus} will be selected by an external input to the design, called Op_Code[1..0];
• the output C[7..0] can be
o loaded back into one of the eight internal registers, or
o read externally.
please help me i have no idea how to create 8 8 bit alu,can someone gv the code for this task plzzz

 

[Marcel Majoor]

ftopic357991

You have to split up your problem into individual parts:

1. the ALU itself (doing and/or/plus/minus)
2. the multiplexer (based on the opcode)
3. ....
4. ....

And then try 'solving' them part by part. Here are the easiest parts:

Solution 1:

  signal port_a   : std_logic_vector(7 downto 0);
  signal port_b   : std_logic_vector(7 downto 0);
  signal port_c   : std_logic_vector(7 downto 0);
  signal alu_and  : std_logic_vector(7 downto 0);
  signal alu_or   : std_logic_vector(7 downto 0);
  signal alu_plus : std_logic_vector(7 downto 0);
  signal alu_minus: std_logic_vector(7 downto 0);

.....
  alu_and   <= port_a and port_b;
  alu_or    <= port_a or port_b;
  alu_plus  <= port_a + port_b;
  alu_minus <= port_a - port_b;

Solution 2:

  signal opcode   : std_logic_vector(1 downto 0);

....
 with opcode select
    port_c <= alu_and   when "00",
              alu_or    when "01",
              alu_plus  when "10",
              alu_minus when "11",
              port_c    when others;

Above takes care of the ALU 'internals'.

 

[mar mar lwin]

mar mar lwin 8 8 bit register

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY alu8bit1 is
port(port_a, port_b : in std_logic_vector(7 downto 0);
opcode : in std_logic_vector(1 downto 0);
zero : out std_logic;
s_1 : in boolean;
port_c: out std_logic_vector(7 downto 0));
END alu8bit1;
architecture behavioral of alu8bit1 is
signal alu_and : std_logic_vector(7 downto 0);
signal alu_or : std_logic_vector(7 downto 0);
signal alu_plus : std_logic_vector(7 downto 0);
signal alu_minus: std_logic_vector(7 downto 0);

begin
process(opcode)
begin
if s_1 then
alu_and <= port_a and port_b;
alu_or <= port_a or port_b;
alu_plus <= port_a + port_b;
alu_minus <= port_a - port_b;
case opcode is
when "00" =>
port_c <=alu_and;
when "01"=>
port_c <=alu_or;
when "10"=>
port_c <=alu_plus;
when "11"=>
port_c <=alu_minus;
when others=>
port_c <="00000000";
end case;
end if;
end process;
end behavioral;

i have try this program and i got the output but i am not sure if this one 8*8 resgister alu or not?
please explain to me and what is the 3rd and 4th parts ? .thanks a lot for u r help