74LVC86 measuring the phase difference?

[Javert]

I need to somehow measure the difference between the leading edges of two clock signals.
The first thing that came to my mind is the use of XOR GATE.
For the first experiments I used 74HC86 . For a large time difference between signals such as 100ns everything works great if the time difference is shortened still on the output I see that the difference between the signals is shortened up to about 20 ns. Between 20 ns and 15 ns, the change in input no longer affects the output and and below 15ns they no longer appear on the output are nothing the signals are like in phase.
I'm interested in differences from about 2ns
It occurred to me to try faster logic, but

1. Faster than HC is at + 3.3V LVC . Is there any even faster logic for + 3.3V?
2. I'm looking at the 74LVC86A datasheet, but nowhere do I see anything from which it is possible to find out what time differences between the input signals the gate can still project onto the output. I can't search or does anyone care about me except me?
3. Are there any faster xor gates for reasonable money, so I'm not interested in GHz XOR from Analog Devices for $ 160 a piece, but gates to say $ 3

 

[barry]

Can you use ECL? MC10EP08 .250ns

 

[KlausST]

Hi,

The problem is when both signal edges are close.
So why not
* delay one signal by a fixed value (gate, RC, delay line ...)
* or invert one signal (not sure if this gives a benefit)

After low pass filtering the analog value needs to be calibrated. But it could be done automatically.

Klaus

 

[danadakk]

What is the sample rate of the DSO you are using to do the measurement ? Or
the max sweep speed of the analog scope if thats what you have, and its BW ?

Following also shows using cable delay to aid in measurement by using unequal
lengths and swapping cables to effect measurement.

Using scope (DSO) on infinite persistence to compare two channels.....


Regards, Dana.

 

[barry]

Using scope (DSO) on infinite persistence to compare two channels.....


Regards, Dana.

I think a DSO costs more than a logic gate.

 

[danadakk]

I think a DSO costs more than a logic gate.

Seems like logic gate not working, and then what is he going to use to look
at output of logic gate ? Accuracy of measurements at single digit ns speeds,
transmission line PCB layout effects.....

Nah, I like scope.

Regards, Dana.

 

[Easy peasy]

you will need to search for high speed low voltage logic gates to make ( or find ) an XOR to do the job ....

 

[Javert]

In short, just a few notes

Can you use ECL? MC10EP08 .250ns

ECL I want to avoid, the need for negative voltage. Simplicity and elegance disappear, I see it as the last choice

What is the sample rate of the DSO you are using to do the measurement ?

I have an oscilloscope with 8GSa/s, but in this case I used it only as a simple tester, I don't know how to say it just a probe if it moves with something on the wire

For the measurement I used a frequency counter and a function generator with a delay line for the second signal. The counter should be able to capture even 20ps pouls for periodic signals with 74HC86 there was nothing on the output with a time difference on the 2ns inputs.

Yes I may have an error in the measurement or wiring or in the 74HC86 itself. But I think it's a so-called dead zone phase detector, which suffers in particular, but not only detectors with XOR gate.
It is mentioned here or here.
I'm rather surprised that it's standard XOR gates, maybe the 74HC86 isn't listed in the datasheet or at least someone didn't measure it and I can't find out how big the dead zone is

 

[KlausST]

Hi,

least someone didn't measure it and I can't find out how big the dead zone is

There is a delay time and there is the rise/fall time. Both should be given in the datasheet or in the family datasheet.

Imagine:
* for a too narrow pulse ... the output will not even start to rise --> no phase measurement possible
* then for narrow pulses ... the output starts to rise, but falls before the output saturates at full level --> non linear phase measurement
* then for wider pulses ... the output gets full swing --> linear phase measurement

Thus if you delay on signal with a fixed time so thst the XOR output gets full swing at zero input difference, you can measure phase differences around zero. From slightly negative ... zero ... to positive. With good linearity.

Klaus

 

[danadakk]

Whats the model number of your freq counter and signal generator ? Curious as to its specs for trigger delay
between gate enable and its input to count. Maybe a pic of your test jig.


Regards, Dana.

 

[FvM]

Dead time is an application specific parameter, you won't find it in a XOR datasheet. Dead time is caused among other reasons by the NOT gate propagation delay inside the XOR circuit. Propagation delay spec in data sheet gives you a measure of the gate speed, it makes clear that standard 74HC86 is unsuitable for 2 ns measurement.

Because it's only part of the total propagation delay, you can assume that dead time is always smaller than specified propagation delay, may be e.g. 1 ns for 74LVC86A. In so far the device should work for your requirements. To measure smaller time differences around zero, you should absolutely follow KlausST's suggestion of applying an additional delay to one input signal.

You reported that in a certain range of input signal delay, the output signal doesn't change. This is probably due to ground bounce and insufficient power supply bypassing. Similar effects can be expected with all real setups, but depend much on the circuit layout.

 

[danadakk]

Just curious, given you have a scope with 8 GS/s why not do a measurement with it
to aid in tracking down the counter approach issues ? It would also provide skew number
for cable delay quite easily. Its differential delay should be a few hundred ps max chan to
chan, and sampling rate more than adequate to do the measurement.

What is BW of scope ? Model number.....


Regards, Dana.

 

[barry]

In short, just a few notes


ECL I want to avoid, the need for negative voltage. Simplicity and elegance disappear, I see it as the last choice

The part I suggested will run off of positive voltages (PECL mode)