can a latch have setup and hold time violation...

[rakesh_aadhimoolam]

hello;;;;;;;;;

can a latch have setup and hold time violation and to say that what is setup and hopldtime violation for a latch.......

can anyone explain............

thank'z'

 

[tronix]

yes a latch has setup and hold time in a way similar to f/f.

 

[aniketd]

Latch Setup and Hold window appears on falling edge if it's high level sensitive latch or vice versa

 

[anilkumarv]

setup and hold violations of latch are simiilar to setup and hold violations of flip-flop

 

[sree205]

Once again, there are only recovery and removal times for a latch. not setup and hold times.

 

[rakeshnunna]

Yes Sree is right.We term them as recovery and removal and not setup and hold

 

[tronix]

Once again, there are only recovery and removal times for a latch. not setup and hold times.

sree205
Can u give further explanation

 

[shwetarao]

For level-sensitive storage element such as latch, data must arrive a certain minimum time befor clock goes inactive. A setup violation can cause invalid data to be captured by the latch or other level-sensitive device.

Hold time is the time for which the data for the next clock cycle shouldnot arrive or when put in other way, it is the time the data for the previous clock cycle has to be held(without changing) for it to be latched. A violation of hold time occurs when the data intended for the next cycle arrives early and there is a probability for the latch to store this data(intended for the next cycle) for the current cycle .

The need for setup and hold test is because the clock signals are not ideal in the sense they don't have a sharp rise or steep fall. That is the clock pulse doesnot suddenly disappear at falling edge arrival time or doesn't suddenly appear at the rising edge arrival time due to slew tranistion time.

Interval between the setup test and hold test is a timing "region of uncertainity". If the signal arrives in that interval, it might or mightnot get stored into storage element on that cycle

Therefore we must ensure that no data arrives during that interval.

So whether its a flip flop or a latch, SETUP TIME and HOLD TIME are applicable.

Look for the figures in the attachment below.

 

[tronix]

Well everything shwetarao said makes sense to me but iam interested in knowing whats the diffference b/w setup/hold time for a latch and a flip-flop as suggested by rakeshnunna and sree205.

 

[chandhramohan]

hi all ,
I think the below fig. gives a better idea of active high clk latch timing diagram.

Regards
Chandhramohan

 

[bhanuriramesh]

materials uploaded are really extra ordianry

 

[ranga]

Good insight into the question which never satisfies anyone

 

[Jyotshna Mamillapalli]

latch have recovery and removal times but not setup and hold time.