65nm technology minimum gate legth and pitch confusion

[VLSI_Learner]

I was reading a Wikipedia article where I found this one

The 65 nanometer (65 nm) process is advanced lithographic node used in volume CMOS semiconductor fabrication. Printed linewidths (i.e., transistor gate lengths) can reach as low as 25 nm on a nominally 65 nm process, while the pitch between two lines may be greater than 130 nm.[

I have problem understanding this -
1. I believed in, suppose, 65nm technology the smallest gate length is 65nm. But here it says in 65nm technology, the gate length can reach as low as 25nm. Please explain this.
2. What is the pitch referred to here? And what is the meaning of "two lines" described here?

 

[VLSI_Learner]

Please reply this.

 

[Colbhaidh]

I think there is an error in this. In a 65 nm technology, printed linewidths cannot go below 65nm but the effective transistor width or electrical width (Leff) can go as low as 25 nm.

The pitch is just the minimum length of gate + minimum space between gates.