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65nm process voltage limits

borabilgic

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Hi, I could not find the voltage handling limits of 65nm process mosfets. How high VDD can I apply to a 65nm chip and for how long? Thank you.
 

dick_freebird

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Pick a foundry and drill into their docs. Core
and I/O devices can vary between flows, and
"how high" depends on things like reliability
expectations and temperature range (the
lower the Leff, the more foundries push on
reliability and apply "use model" limits in
lieu of old fashioned "full temp range, all
the time" reliability rules.
 

borabilgic

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Pick a foundry and drill into their docs. Core
and I/O devices can vary between flows, and
"how high" depends on things like reliability
expectations and temperature range (the
lower the Leff, the more foundries push on
reliability and apply "use model" limits in
lieu of old fashioned "full temp range, all
the time" reliability rules.
Hi Dick,
Can I apply 3.2V pulses like 1-2ns period(%50 duty cycle)?
 

dick_freebird

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On the drain of a core device that's likely to
cause punchthrough (hot carrier drift at the
least) and at 50% duty probably a lot of self
heating which could be an interconnect
fusing or electromigration threat. It's likely
that gate ox ruptuer will not be the primary
problem as BVox tends to be 2X or more,
rated working voltage even at DC and can
be higher at short pulses where the oxide
carrier percolation "filaments" do not have
time to fully form and do permanent damage.

I/O devices at 3.3V or 5V nominal rating ought
to be fine. Though your I/O devices may not
be capable to work at 500MHz.
 

borabilgic

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Sorry I forgot to write pulses for a duration of 1-2 us for testing puposes.
 

ThisIsNotSam

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you need to refer to the specs, there is no such thing as a fixed voltage for a given technology. although the values you are mentioning sound reasonable, I have worked with 65nm IO cells that took 2.5V nominal but would not work reliably at 3.3V. The foundry offered another IO library that was much more tolerant, taking anything between 2.5 and 5V. But there was a design trade-off there.
 

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