Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
65nm or 90nm this number represent the minimum gate length of the transistor in IC realization.
As this number decrease the technology becomes faster and have a smaller area but higher power consumption. why??
Because if the MOS transistor area decrease that allow us to put more number of transistors inside the same area. And also as the the area of the gate decrease the load capacitance(parasitic) is decreased and so the speed is increased.
So we can say that 65nm technology is more faster and less area than 90nm technology.
For more information about the IC realization technologies visit
I think the poster before me mispoke. As the minimum feature size of ICs decreases the power consumption does not increase, but the power density does. The power consumption will still decrease for a comparable design, but it will be in a much smaller area so the density of power dissipation will increase.
technology is specified in terms of minimum gate length possible in a particular process technology. As the gate length decreases the distance e needs to travel from source to drain becomes less & hence the device becomes faster.. Before all these gate lengths were mentioned in terms of micron lengths, but now its in nanometers. Gate lengths less than microns are typically called Deep Submicron technolgies(DSM). As the technology goes more into DSM lot of other parasitic elements needs to be considered will designing. For example in a micron technology the scenario was like, the propagation delay of a circuit (involoving transistors) were more than delay added by the wire connecting this circuit to something else. But in a DSM process delay of the circuit is less than the one added by the wire. Hence in a DSM delay added by the wire lengths is critical while in a micron technology that was mostly immaterial. Infact citing this example only MAGMA introduced their concept of synthesis.
I wonder any of you have a rule of thumb for the transistor sizing, current, gm, Vt for each 90, 65 and 45nm process.
What will be the rise time and other parasitic capacitance or conductance that is scaled with the technologies. is the any limitation of the highest frequency each technology can go