555 as vco schematics..

[carsein]

Hi,
Right now I'm given a small project by my lecturer to do a vco from 555 timer. The centre frequency of the VCO is 10 kHz. I've already read the application note of the 555 timer and tried to simulated it with pspice. There are 2 problems occur when I try to simulate it:
1) There is a delay in output waveform. How can I make it start exactly at 0 s?
2) I've followed all the calculation from the application note. But I don't get 50% duty cycle and the frequency is not 10 kHz.

I hope you guys can help me with this. Here I attached the result of output waveform of the 555 timer.
View attachment output waveform 555.bmp

 

[andre_luis]

carsein,

Could you post this AN ?

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[carsein]

carsein,

The frequency of oscilator is defined by similar edges ( rising or falling )

The picture you posted seems having a duty of 50%.
You must remember that even uC oscilators haven´t an exact 50 duty.



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oh..it's indeed 50% duty cycle??sorry i'm very newbie to this..
and do you know, why there is a delay at the output waveform??

 

[andre_luis]

Some application notes are not precise, and are concerned just for first approximation.
If possible, post link of IC manufacturer AN here...

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[carsein]

here is the App. note:
**broken link removed**

 

[KJ6EAD]

There is so much literature available on the internet for the 555 timer that I question anyone's research abilities when they ask about it here; does google not work where you are?

Nevertheless, I will offer two hints in reference to the application note you have: 1. select component values to make the oscillator center frequency 10kHz when the control voltage is 65% - 70% VCC, 2. VCO and voltage-to-frequency conversion are similar concepts.

 

[carsein]

thanks for your hint..for the above picture(1st post)..i only connect a capacitor to the control voltage..

and below is the picture of the output waveform after i connect a pulse voltage to the control voltage..
its looks better than before..but still there is a delay..

View attachment output 555 with cv.bmp

 

[andre_luis]

here is the App. note:
**broken link removed**

carsein,

Unnafortunatelly, this document does´t bring informations about range of output current.
This tolerance could explain your imprecise result.

Concerning delay, it is suposed expected, due just before power-on, circuit is not energysed

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[carsein]

carsein,

Unnafortunatelly, this document does´t bring informations about range of output current.
This tolerance could explain your imprecise result.

Concerning delay, it is suposed expected, due just before power-on, circuit is not energysed

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Thanks for your concerned..Now I understand why there is a delay..The timer takes time to produce the output waveform..Thanks again

 

[FvM]

I don't understand, why a time offset in output waveform should be a problem. It's just, how the device works.

In the application note, there's only one VCO circuit, although it's not name as such: Figure 13, "Pulse Position Modulation". You'll find it with clearer waveforms in the 555 datasheet. But according to 555 properties, you can't achieve a constant duty cycle with variable frequency.You didn't tell about the intended frequency range and duty cycle, so I can't determine, if it may be acceptable to set the duty cycle to 50% for center frequency.

 

[carsein]

I don't understand, why a time offset in output waveform should be a problem. It's just, how the device works.

In the application note, there's only one VCO circuit, although it's not name as such: Figure 13, "Pulse Position Modulation". You'll find it with clearer waveforms in the 555 datasheet. But according to 555 properties, you can't achieve a constant duty cycle with variable frequency.You didn't tell about the intended frequency range and duty cycle, so I can't determine, if it may be acceptable to set the duty cycle to 50% for center frequency.

for the time offset, it's my misunderstanding..sorry for that
I design my circuit just like figure 6. The intended lock-in frequency range is 9.5 kHz - 10,5 kHz.

 

[KJ6EAD]

Have you considered reading other data sheets, for example: **broken link removed**?

 

[FvM]

Figure 6 is not discussing a frequency control input. Figure 9 c gives the calculation for figure 6, assuming a nominal control voltage of 2/3 VCC. If you change the control voltage, the duty cycle will change, too.

 

[carsein]

Figure 6 is not discussing a frequency control input. Figure 9 c gives the calculation for figure 6, assuming a nominal control voltage of 2/3 VCC. If you change the control voltage, the duty cycle will change, too.

yes..for the simulation I used the calculation from Figure 9c..
My Ra=Rb=7.5k Ohm and C= 10nF

---------- Post added at 23:36 ---------- Previous post was at 23:11 ----------

Have you considered reading other data sheets, for example: **broken link removed**?

Thank you. I'll take a look at this data sheets.

 

[andre_luis]

...If you change the control voltage, the duty cycle will change, too...

Probably just at a certain value of output the duty will be exact 50%, due to non-linearity of capacitor charge.

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