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how does the output stage of this opamp function?

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wholx

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the opamp is used as a buffer in a mixed-signal circuit. the input stage is composed of two differential pairs (folded-cascode) to achieve high input CM range. my quesiton is about the output stage, i guess PP15 and NP3 are used to avoid the class B output PP14 and NP4 blocked at the same time, but i'm not sure. anyone can explain how exactly do pp15 and np3 work in the circuit?
 

I've never seen this kind of circuit before, but at first glance it appears to have 2 stable operating points.

Assume our differential input is 0. Therefore the current source above and below PP15 + NP3 are the same. Since PP15 and NP3 are common-gate type buffers, we have several stable operating points. All the current could go through PP15 with it's drain voltage being sufficiently high as to cut off NP3. On the other hand, all the current could go through NP3 by having it's drain voltage sufficiently low as to cut off PP15. So the only way we don't get multiple stable operating points is if we include the Rout of the current sources. If both current sources Rout would be identical, then the current would split evenly amongst both common-gate amplifiers (PP15 and NP3). Unfortunetaly the Rout of a PMOS is not necessarily the same as that of an NMOS, so depending on what process corner you're in, the current could split in an unpredictable way....

Now am I missing something? Did I misread the schematic?

o.k. Let's assume for now that the op-amp will servo the current so that it splits evenly (or close to). At this point, it's fairly easy to see what's going on.

Lets say the top current source is driving 1uA more current then the bottom current source. The voltage on the bottom current source will have to rise so that it's Rout will shunt that extra 1uA current. The voltages on the current sources vary by gm*Rout. That voltage variation is connected to the gates of the output drivers.

PP15 and NP3 are there so that the quiescent voltage on the current mirrors will create a pre-defined quiescent current through the output stages.
 

it is a class ab output while the whole circuit is a rail to rail opa.
the pp15 and np3 function:
Vgspp15+Vgspp14=Vgspp8+Vgspp13
Vgsnp3Vgsnp4=Vgsnp10+Vgsnp19.
which make sure the output work in class AB
 

Hi Sunking,

Can you give a more detailed explanation? Why that two conditions can gurantee it's class AB operation?
 

Class AB control is reached through a translinear loop. Control transistors, np3 and pp15, are driven by a N mirror and a P mirror. Diode connected transistor set the bias point of control transistors.

Notice that N and P mirrors are complimentary, that is, when one of them increases the current, the other one reduces its current.

So, for exmaple, when the N mirror puts more current, source of np3 goes down making the N-type output transistor to shut off. On the other hand, the P mirror puts less current, which cuts pp7 and then its source node gets high impedance. This allows the drain of np3 to go down, pushing from the gate of the P-type output transistors, making it to conduct more current.

The dual behavior occurs when the N mirror reduces its current and the P mirror putsq more current through the controls transistors.

Compensation is Miller-like. You must determine the capacitors in both cases when the N output transistor is on (P off) and when the P is on (N off).
 

Here, PP15 and NP3 form a floating current source
 

thx everybody, but can anyone explain a little more about translinear loop?

i found another application using floating current source on google book search.
 

Hi chen_Analog

In no way PP15 and NP3 make a floating current source as they are being driven by current sources. They are not able to change the current through the branch.

A translinear loop get stablished when you can fing a closed path containing only Vgs. In the first figure NP19-NP10-NP3-NP4 form a translinear loop. There is also another one with P-type transistors.
 

This is a rail-to-rail OPAMP with constant-gm control (on the left part of the circuit which you didn't shown). Output is class-AB mode.
This circuit is designed by a Dutch PhD Ron Hogervorst. His PhD thesis can help you (I don't known where to download it. It's also published as a book). But I think the previous reply already gave you an explanation.
 

Is that translinear working with exponential relationship only? Here it has diode connected device, but is still with square-law. Correct me if I am wrong, please
 

nxing,

As I know, the tranlinear loop works with square law as well as exponential relationship. There is a book discussing tranlinear circuit uploaded in this board,but I cannot remember its name, you can search it yourself.

BTW, PP15 and NP3 acts as floating voltage source instead of floating current source.

regards,
jordan76
 

but it is difficult to understand.
 

Humungus said:
Class AB control is reached through a translinear loop. Control transistors, np3 and pp15, are driven by a N mirror and a P mirror. Diode connected transistor set the bias point of control transistors.

Notice that N and P mirrors are complimentary, that is, when one of them increases the current, the other one reduces its current.

So, for exmaple, when the N mirror puts more current, source of np3 goes down making the N-type output transistor to shut off. On the other hand, the P mirror puts less current, which cuts pp7 and then its source node gets high impedance. This allows the drain of np3 to go down, pushing from the gate of the P-type output transistors, making it to conduct more current.

The dual behavior occurs when the N mirror reduces its current and the P mirror putsq more current through the controls transistors.

Compensation is Miller-like. You must determine the capacitors in both cases when the N output transistor is on (P off) and when the P is on (N off).



OK THIS EXPLAINATION WAS VERY HELPFUL. BUT MY OPAMP IS WORKING AT BIAS CURRENT OF 1 uA AND CASCODE BRANCH OF THIS OTA CARRIES 1.5uA. WITH THESE LOW CURRENT I AM NOT ABLE TO BIAS CLASS AB OUTPUT STAGE IN SATURATION REGION.
IS IT OK TO BIAS CLASS AB STAGE IN SUBTHRESHOLD REGION ???
WHAT SHOULD BE THE TYPICAL QUIESCENT CURRENT VALUES FOR SUCH A CLASS AB STAGE ?
 

can anyone explain how to determain the output swing of this circuit
i am really confused
thanks in advance
 

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