[50 pts] Delay Calculation

[mouzid]

Hello

My goal is to calculate the delay from of A to C and from A to F.
I have to calculate the equivalent Capacitors Ceq and Resistors Req at each time. My problems is that the MOS has many capacitances (cgs,cgd,cgb,csb and cdb) and when I use it to construt the circuit above I can't calculate Ceq and Req.
Could you please help.
Could somebody share a material/Tutorial showing how to do That.

Danke.

 

[doibongvui]

The delay (best case or worse case) depends on A or B input switch. I attached the link shows you not only know how to calculate delay of nand/nor/inverter but also teach you how to do good sizing transistor in design

**broken link removed**

Good luck

 

[erasmocf]

Here you must calculate the capacitance of each node of the circuit and use a well known equation called Elmore's Delay Model. This equation gives a rough aproximation of the circuit delay, once it don't consider the transistors input slope.

In your circuit you will just calculate two cases: the rise and the fall times - both with B and D at high level.
Using the Elmore's model you must calculate the delay from A to C, C to E and E to F and make a sum of it all.

In the internet you can find a lot of material showing how to calculate using the elmore's model. In you case the equations of output's rise and fall will be:

tau_rise = Cout1*(R_An + R_Bn) + Cout2*R_Cp + Cout3*R_En
tau_fall = Cout1*R_Ap + Cout2*(R_Dn + R_Cn) + Cout3*R_Ep

Cout is all the capacitance atached to the output node (gate and intrinsec capacitances).
tau is the time to the output to reach 63,2% of Vdd. To find the the time to reach 50% you must divide the value by 1.4426. If you want to know the slope (time spent by the output to reach from 10% to 90%) you mus multiply the tau value by 2.1972.

I think it is.

 

[mouzid]

Ok I see,
How to calculate the equivalent capacitances and resistors at point C, E and F ?

 

[erasmocf]

The capacitances in the nodes are the sum of the drain capacitances of each transistor connected to the node.
The drain capacitance in this case is considered to be just the diffusion capacitance (pn junction capacitance), so:

Cd = Cdb, where
Cdb = Cbotton * Ad + Csw * Pd

Cbotton is the capacitance at the botton pn junction in the drain [F/cm^2].
Ad is the drain area
Csw is the sidewall pn junction capacitance [F/cm].
Pd is the perimeter.

About the resistances: they depends upon the operation point of the transistor. In your case you have to use a Req that is the average value of the resistance over the operation region or use the resistance in the linear region given by:

R = 1 / ( µ * Cox * (W/L) * (Vdd - Vth) )

Added after 13 minutes:

Correction:
in the sum of capacitances you must add the gate capacitance of the gates connected to the nodes.

 

[mouzid]

What about the other capacitances Cgs, Cgd, Cgb,Cds etc..Why they are neglected ?

 

[erasmocf]

In you circuit you have just two vector variations to change the value of F:
ABD = 111 to ABD = 011 (F falling)
ABD = 011 to ABD = 111 (F rising)

The capacitances are neglected because the nodes that they are attached don't have voltage variation or because in the region the transistors are operating this capacitances are neglected. A reference is Rabaey - Digital Integrated Circuits (2nd edition) pages 109 to 111.

regards