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4 questions for finalizing clock design

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geozog86

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Hello! I am designing a clock, and i have some questions before moving to the layout part

1--i want to be able to drive a big (12p) load. My most "correct" node to take the output is the comparator output, but i don't want to load it so heavily. So what do you think would load my comparator output as little as possible and be able to drive such a load? Just an inverter? A latch? (i have symmetrical outputs on my comparator)

2--i want to simulate and check my jitter and my phase noise. I mostly find in the internet special equations and theory, and no practical help on cadence: which analysis for example? On a simple clock signal (i see special help when designing a VCO or a PLL....i just have an RC oscillator!)

3--i will have to perform some trimming and my idea is to be able to choose from a number of different voltages for my threshold (used for comparison). Do you know any block that can transfer analogue info from input to output? I guess all the blocks (like multiplexers) in my libraries are digital....sounds childish but i'm confused!

Any of the above you can give me an idea about, thx in advance :)
 

dhaval4987

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1. your comparator can either drive a chain of tapered inverter- also known as tapered buffer. That generally drives bigger loads with improvement in delay. If you wish to drive even larger load- try reading about Hidh Drive Buffer- i drove 1nF cap using that. But in your case- I guess tapered buffer should help you..

2. for jitter analysis- export the output of transient response (you will see it in .csv forma) into excel sheet and then you can simply calculate Absolute, Cycle to cycle and periodic jitters in excel.

3. even i am confused- but you can use switches and control switched using mux. A switch is either on or off. So that way Mux can control it and on the input of switches apply analog signals. not sure though- but worth trying.

Regards,
 

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