Help understanding ON/OFF latching power

[rompelstilchen]

Hi,

I try to understand this

www.mosaic-industries.com/embedded-...projects/raspberry-pi/on-off-power-controller

it seems like a simple schematic, but all these caps additional and resistors complicate everything to me

I dont really fully understand what voltage occurs where and when

can someone give me a step by step explanation ?

thanks

 

[d123]

Hi,

I think (I don't know about the Pi pins in that schematic, not sure to what extent it matters 'though):

1) PMOS held high by I'm guessing 100k.
2) 10k + 1uF should be a debounce circuit for the pushbutton mechanical ringing/bouncing.
3) Other 100k and 1K are 5V divider for NMOS gate.
4) 10uF, not sure, maybe smoothing capacitor, possibly not 'though.
[5) this is obvious, I think - user defined "on" at power-up or "off" at power-up]

I guess - when the pushbutton is pressed, the PMOS gate is pulled low/to ground, which in turn turns on the NMOS, which latches the PMOS on...which latches the NMOS on..., so the circuit stays on until the next pushbutton press. Guessing very much, the second time the button is pressed the - I'm not at all sure this is correct - the 100k somehow pulls the PMOS high, and in turn, turns off the NMOS, not sure what the 1uF does at that precise moment, or the diode in general, perhaps 1uF discharges to ground (and diode prevents it from discharging into Pi pin #7), creating the path for the 100k to pull the PMOS gate high, so it goes low and cuts off voltage to NMOS gate, so that goes low, and circuit stays latched "off". Hope I'm not talking too much rubbish.

 

[rompelstilchen]

the whole idea is to create some sort of ATX kind of behaviour

push, turns it on,
puch again triggers a 5v to GPIO pin through 1k res, wich in turn launch a script that change the GPIO pin as output and is set low to turn off power supply
pushing >3 sec force shuts down

PMOS held high by I'm guessing 100k.

so you mean after the 100k, potential is 0V right ?

Other 100k and 1K are 5V divider for NMOS gate.

actually the 1k is there to protect GPIO wich is used as input then as output(LOW) - for software shutdown script

10uF, not sure, maybe smoothing capacitor, possibly not 'though.

the whole 100k/300k/10µF, I really dont get

I think 100k+10µF is used to pass the voltage rise to the N-MOSFET (but why a 100k res here ? )
while 300k+10µF are there for the long press - shutdown process

I found the explanation here, but I really cant put the puzzle together, cos they bring a lot of different examples

http://www.mosaic-industries.com/em...n-switch-turn-on/latching-toggle-power-switch

 

[d123]

Hi,

Thanks for the explanation about the GPIOs, function of the circuit with a Pi.

"so you mean after the 100k, potential is 0V right ?" - Not sure what you mean. It depends on "auto-on" or "auto-off". I'd say, no, 100k is connected to V+ and its other end to the NMOS drain + PMOS gate so with "auto-off" they are all at a high potential; when button pressed this junction is connected to ground via the 1uF capacitor so thay all go to a low potential at that moment. Again, I'm guessing, based on another debounce circuit I know - that the 10k + 1uF are the debouncing elements. The 100k holds the PMOS gate high (off) until the button is pressed, making the connection to ground "stronger" than the 100k to V+, so the PMOS is pulled low and can turn on.

"the whole 100k/300k/10µF, I really dont get" - me neither, presumably those values work for the timing used in that circuit. 10k * 10uF is a theoretical 1 second. I'll just quote from the Mosaic description:

"Subsequently, a long button touch turns the circuit OFF. Pressing and holding the button down pulls down the gate of the low-side MOSFET after a few second delay determined by the discharge of the 10μF capacitor through the 300 kΩ resistor. The low-side MOSFET turns OFF, allowing the gate of the high-side MOSFET to rise to its source voltage, turning it OFF too."

 

[cjdelphi]

I'd be tempted to use a flip flop instead