Why is our Vgs waveform distorted when seen with Diff probe?

[treez]

Hello,
Please explain why our high side fet Vgs waveform looks distorted when we look at it with a Diff probe. The waveform drawing is attached. It only looks distorted when we hook up the input voltage (400v).
We are using a Lecroy ADP305 diff probe to view the high side FET waveforms of our 300W Buck SMPS. We plug the diff probe into a Lecroy waverunner 64xi scope.

(Buck vin = 400v, vout = 100v, pout = 300w)

Lecroy ADP305 Diff Probe….
https://cdn.teledynelecroy.com/files/manuals/adp30x_om_e.pdf

Lecroy waverunner 64xi scope user manual
https://cdn.teledynelecroy.com/files/manuals/wrxi_om_revc.pdf


Also attached is the buck schematic and its ltspice sim

 

[D.A.(Tony)Stewart]

Page 10 of ADP specs seem to indicate you are operating beyond safe limits. The problem is likely due to leakage capacitance in the isolation.

 

[FvM]

There's no first-sight indication why the differential probe shouldn't be used for this measurement. It might be a problem of transient common mode overload or simply a defective probe.

I know that Lecroy ADP and similar probes are working at higher voltages without problems (e.g. switchers with 700V bus voltage).

Facing a similar problem, I would check
1. if it's caused by common mode signals (operating the probe with shorted input)
2. if it's an overload problem (starting above a certain CM voltage or dV/dt level)

3. consult with the vendor, possibly return the defective device

 

[D.A.(Tony)Stewart]

This is a good choice of instrument but a bad choice of use.

Short both diff probe inputs to measure CMMR at your various test points and see how the choice common mode probe ground available is affected by CM input noise from your noisy PFC design.

It is not a question of bad instrument, but bad understanding of limitations of active high speed dff probes and CMRR.

If you cannot get a flat line, with both inputs connected to same input signal then the choice of CM signal or ground is exceeding CMRR limitations of the probe design (3% or 30dB @ 10MHz) So change CM ground reference for the probe using ferrite around CM signal wires or ground or change probe input ground point to average CM voltage instead of 0V or use active guarding.

Understand the source. Then the solution is obvious.

It is not the 400VDC isolation that causes the problem but the high AC high frequency CM noise and your use of the excellent probes. that is the problem.


I recall engineers who did not observe the very low ESD limits of FET buffered Diff probes blew the FETS easy . Our Tek Diff probes had a limit of 25V , yours is better but still needs to be used with caution.