Differential Quadrature Signal Generation of Low Power

[pancho_hideboo]

I would like to generate fully differential quadrature signals of 950MHz using PLL Frequency Synthesizer from 1900MHz differential VCO with low power.

Currently, I realize this by D-FF based on master-slave latch structure using CML.
However current consumptions are fairly large.

Alternate idea I have is using two D-FFs based on TSPC where one is rising edge triggered and the other is falling edge triggered. And I use two inverters and two buffers after them for generating fully differential quadrature signals, i, ib, q and qb.
However this scheme is pseudo differential.

Quadrature VCO can not be candidate.

I use 0.15um-CMOS of vdd=1.5V.

If you know good technique, could you share it with me ?

 

[dick_freebird]

What about (say) 4 CML stages with a phase-flip at
one point, control the speed by the tail bias and
take off your signals at the #2, #4 horns (dummy
load #1 and #3 equally), put the phase-flip between
#4 and #1. Might do this with ECL and varactor loads
if you have to buy piece parts and not masks / wafers
(SSI CML parts being not so common, but perhaps
sourceable?).

Now you might, or might not, consider ECLiPSe gates
"low power"....

 

[pancho_hideboo]

What about (say) 4 CML stages with a phase-flip at one point,
control the speed by the tail bias
and take off your signals at the #2, #4 horns (dummy load #1 and #3 equally),
put the phase-flip between #4 and #1.

What architecture do you mean ?

Now I use well known structure I attached as figure.
And I control tail bias current of them.

consider ECLiPSe gates "low power"....

What do you mean by "ECLiPSe" ?

 

[dick_freebird]

There was a family of higher-speed ECL parts (back
in the day) - "ECL in pS" - marketing tag. May have
gotten the spelling slightly wrong.

You structure looks sort like what I was thinking,
those are MOS CML gates. You might find some
frequency upside in a SiGe implementation (at a
significant cost). The text implies this is a clock
divider, not oscillator per se. But a ring of 4 CML
inverters, flip once, will be a ring oscillator that
can be tail-current-controlled across some range.

If you can, more stages may make oscillation
more robust.