[Moved]: CS Stage with current-source Load

[anhnha]

I am having a problem understanding CS stage with current-source load in Design of Analog CMOS Integrated Circuits by Razavi.
This is a sentence from the book:

"We should remark that the output bias voltage of the circuit in Fig. 3.1.4 is not well-defined."
Could you explain it in detail?

 

[SpiritMicro]

I try to make you understand
"We should remark that the output bias voltage of the circuit in Fig. 3.1.4 is not well-defined."
this means that the output of the node Vout can not be easily determined .for example
if the dc value of Vout is in the range of Vsatm1<Vout<Vdd-(|Vsatm2|).both the M1 and M2 in the saturation region
also since the gain of the CS is so large, that you alawys don't exactly know where Vout is unless using feedback

 

[arya.jagadeesh]

mosfet is voltage controlled current source...

so situation here is like you have two current sources in series...if you write kcl...some of entering cuurents at particular node is equal to sum of leaving currents..will be true only if values of current sources in series are equal..suppose if lower current source is higher than upper one...you are taking more charges from lower current source and voltage will become negative...if upper current source is higher than lower one...you are putting more charges and voltage becomes high...

now coming to circuit ...at particular temperature and corner this circuit will work..but with varying temp and corner vt ,gm etc will change ultimately resulting in change in current..it happens that this change is not same in both current sources so..voltages at the output becomes either very high or negative...so we say voltages is not well defined..to control these kind of nodes(high impedance nodes) you need some feed back loop

 

[anhnha]

Thank you.
Sorry but I couldn't understand the answer.

 

[anhnha]

CS Stage with current-source Load: large signal analysis

Could anyone help me do the large signal analysis for the circuit below?
I want to hand plot Vout vs Vin.

 

[buffallo]

Hi,

you may also consider this circuit as a 'current comparator'.
Esentially, the Vout vs Vin plot will be really similar to that of an inverter, but the triggering voltage will be shifted (determined by the sizes of the devices and the bias voltage of M2).
Really, the output is High impedance and the exact voltage will be hard to be defined.

For the small analysis itself, I think it should be something like:
Vout = Vin*gm_m1 * gds_m2

Since gds tends to be big, the gain of the circuit will be big. This means that the output is very sensitive to
small variations of every parameter, making it somewhat not useful for manufacturing (without feedback).