32BIT Register file code in vhdl

[DIVYA SUDHA]

hi friends ....I Have problem in executing the following 32bit register file code in VHDL. So anyone suggest me the coorections in the following code plz

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity regfile is
Port ( Ra : in std_logic_vector(4 downto 0);
       Rb : in std_logic_vector(4 downto 0);
       Rw : in std_logic_vector(4 downto 0);
    RegWr : in std_logic;
      clk : in std_logic;
      busW:in std_logic_vector(31 downto 0);
     busA : out std_logic_vector(31 downto 0);
     busB : out std_logic_vector(31 downto 0));
end regfile;
 
architecture Behavioral of regfile is
type reg_file is array (31 downto 0) of std_logic_vector(31 downto 0);
signal regarray:reg_file(0 to 31):=(x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000",x"00000000");
begin
process(Ra,Rb,Rw,RegWr,clk,busW)
variable addr_a,addr_b,addr_w:integer;
begin
addr_a:=CONV_INTEGER(Ra);
addr_b:=CONV_INTEGER(Rb);
addr_w:=CONV_INTEGER(Rw);
busA<=regarray(addr_a);--Read R[Ra]
busB<=regarray(addr_b);--Read R[Rb]
if (clk'event and clk='1') then  ----wait for active clock edge
if (Regwr='1') then --—see if write signal is active
regarray(addr_w)<=busW;--write the data
end if;

---

end if;
end process;
end Behavioral;

 

[imbichie]

Can you paste your problem here..?

Is the problem during the simulation or synthesis..?

Or is it a logical problem...?

 

[TrickyDicky]

take the busA and BusB assignments out of the process, and move the variable assignments into the clocked if branch for a start.