joe345
Newbie level 1
32 bit alu design
Trying to perform addition on the op code 010 but i cant use + sign as the requirement for addition so im trying to perform it using a ripple carry half bit adder but i dont think my loop is ok. Because if i perform 011 + 111 i do get correct result.. any suggestions?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cout : OUT STD_LOGIC;
zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS BEGIN
SIGNAL carrytemp: std_logic
PROCESS(a,b,op)
BEGIN
carrytemp <= '0'
CASE op IS
WHEN "000" =>
result <= a AND b;
WHEN "001" =>
result <= a OR b;
WHEN "010" =>
for i in 31 downto 0
result(i) <= ((a(i) XOR b(i))+carrytemp);
carrytemp <= a(i) AND b(i);
end loop
cout <= carrytemp;
WHEN "110" =>
WHEN "011" =>
result <= a;
WHEN "111" =>
result <= b;
END CASE;
END PROCESS
END description;
Trying to perform addition on the op code 010 but i cant use + sign as the requirement for addition so im trying to perform it using a ripple carry half bit adder but i dont think my loop is ok. Because if i perform 011 + 111 i do get correct result.. any suggestions?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY alu IS
PORT(
a : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
op : IN STD_LOGIC_VECTOR( 2 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cout : OUT STD_LOGIC;
zero : OUT STD_LOGIC);
END alu;
ARCHITECTURE description OF alu IS BEGIN
SIGNAL carrytemp: std_logic
PROCESS(a,b,op)
BEGIN
carrytemp <= '0'
CASE op IS
WHEN "000" =>
result <= a AND b;
WHEN "001" =>
result <= a OR b;
WHEN "010" =>
for i in 31 downto 0
result(i) <= ((a(i) XOR b(i))+carrytemp);
carrytemp <= a(i) AND b(i);
end loop
cout <= carrytemp;
WHEN "110" =>
WHEN "011" =>
result <= a;
WHEN "111" =>
result <= b;
END CASE;
END PROCESS
END description;