2D DCT architectureby using distributed arthemetic

[cedance]

2d dct

hi,

i am in need of a 2D DCT architecture that can be effectively reconfigured. i mean i am trying to implement the DCT compression of images on an FPGA kit. i am trying to make it reconfigurable. could any one help me pls! i ned some ieee papers also on it...

thanks..


/cedance

 

[yygetit]

vhdl code dct

I attacted 3 papers for DCT implementation.
M.T Sun's paper is most fundmental and easy to implement because of the regularity. it has pipelined arch, and can be reconfigurable.
Also can be used DCT/IDCT.

 

[cedance]

2d dct +vhdl

I attacted 3 papers for DCT implementation.
M.T Sun's paper is most fundmental and easy to implement because of the regularity. it has pipelined arch, and can be reconfigurable.
Also can be used DCT/IDCT.

is there a direct VHDL code available, any ip core??? it would be better.. i find that paper what u referred easy to implement is 1989 paper.. and reconfigurability issue is around the 2000 to 2003... so i think there would be better implementations available. if any1 could get me a VHDL code!


/cedance

 

[Vonn]

architecture to implement dct

cedance, Have you found what you are searching for , If yes plz post it as Iam also in need of IDCT vhdl code

 

[liurong82]

vhdl code for dct

kanbudao