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I don't know the process you use so i can't absolutely say where is the correct termination (sub or gnd) of the third terminal of your cap.So,take a look
at the tech manuals and see their instructions or furthermore contact your pdk support for more help.
The answer is NO definetely.Your thought is just a "cooking" of the results...Try to come to the expected results via the correct way and not with cheating ;-)
The process is XFAB. If the capacitor has only 2 terminals in the layout and LVS is OK. What can be wrong if the capacitor substrate (in schematic) is floating?
I suppose that you mean the usage of the vncap_inh that has two terminals,right?If this case suits you go on with this.The inh means inherited connection that is the model has already done the connection to the substrate or wherever else for you.
In case of a capacitor with 3 terminals dig into the manuals or contact pdk support team for more info as i said before.Unfortunately,i am not familiar with this tech and i can't assist you more on this.
What can be wrong if the capacitor substrate (in schematic) is floating?
It is like the model is not working properly,not producing all the effects that this connection/terminal implies (like parasitics etc.)..Additionally the substrate of the capacitor is not properly biased as you would do for a nmos transistor for example.I think you can understand this
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