3 order delta sigma modulator in Matlab and Verilog

[strennor]

Hi All,

It has been a long time I read articals, download files, learn your experience here. Now it is time to share something.

I just learned some delta-sigma modulator and did a simple Simulink model in Matlab with 32-bit realization, then a Verilog code 24bit realization with testbench.

A beiefly documentation is attached.

If any you delta-sigma expert give any advice, I will be more than happy.

Enjoy it!

Regards,
Strennor

 

[ipyd]

Thank you very much..
I really appreciate your work...
Now, i'm studying this sigma delta modulator, but i still have no idea how to implement it.
I'll try your code.. and I'll ask you if I have a problem..
Thanks..

 

[frankwen]

goog guy
veryuseful
thank u very much

Hi All,

It has been a long time I read articals, download files, learn your experience here. Now it is time to share something.

I just learned some delta-sigma modulator and did a simple Simulink model in Matlab with 32-bit realization, then a Verilog code 24bit realization with testbench.

A beiefly documentation is attached.

If any you delta-sigma expert give any advice, I will be more than happy.

Enjoy it!

Regards,
Strennor

 

[ptoo]

thank you good doc
I appreciate you if you advice me the sigma delta fractional PLL

 

[semon]

Thank you very much..
I really appreciate your work...
Now, i'm studying this sigma delta modulator, but i still have no idea how to implement it.
I'll try your code.. and I'll ask you if I have a problem..
Thanks..

 

[Maidabino]

hanks alot.

 

[ahball]

good,thanks!

 

[IFadeToGrey]

Hi Strennor,

Thanks for posting this. I'm still trying to wrap my head around how Delta-Sigma DACs work. Why is the output four bits instead of one, and how does it relate to the offset?

TIA

 

[IFadeToGrey]

Can anyone help to give me some insight on this?

Thanks.

 

[tupadupa]

Thanks for sharing! Nice example.

In the digital DSM version I would change all data types (in adders, conversion blocks) to signed integer and remove the quantizer.

 

[xabarov]

In the digital DSM version I would change all data types (in adders, conversion blocks) to signed integer and remove the quantizer.

Yes, I am going to do it too. Signed types are more flexible, I think. It can be useful if you would like to change width of accumulators.

Did anyone tried to simulate verilog using 24 bit fullscale input signal? Looks like modulator is overloading and become unstable. What is a input range for this modulator`s 24 bit implementation?

In real world implementation, should we avoid overflow using saturating adders?

Please, share your experience.

 

[wonbef]

thank you very much! now i am looking for it

 

[skyenew]

so cool!!~~~

 

[pankaj jha]

Hi All,

It has been a long time I read articals, download files, learn your experience here. Now it is time to share something.

I just learned some delta-sigma modulator and did a simple Simulink model in Matlab with 32-bit realization, then a Verilog code 24bit realization with testbench.

A beiefly documentation is attached.

If any you delta-sigma expert give any advice, I will be more than happy.

Enjoy it!

Regards,
Strennor

Dear Strennor,
Thanks for uploading the code. but I think this code is suitable only for real sigma delta modulators.
I need a MATLAB code to plot the PSD for a quadrature sigma delta modulator. Can u provide the same to me???