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3 bit flash adc circuit and its corresponding waveform

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Aritra17

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pls mail me a 3bit flash adc circuit and its corresponding waveform

i'm doing this project in tanner eda

i have got the comparator output good

but i can't figure out the whole circuit&i dont know what will be its output

searched through google a lot, but couldn't get any useful information
pls help
 

leo_o2

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3-bit Flash ADC just needs 2^3=8 comparators. Then add a encoder to generate 3-bit output from outputs of 8 comparators.
 

wanghs1986

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I think you need some basic understanding of ADC. First sampling and quantization then switch to concrete ADC architecture
 

Aritra17

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i have completed adc schematics in tanner eda software
for 3bit adc
i have used 2^3 resistor i.e 8
(2^3)-1 comparators i.e 7
then as thermometer encoder i have used xor gate
then the xor output is being feed to a 3bit encoder

but there is a confusion
many says 2^3 comparators for 3 bit adc
also some says use some other gates but not adc
whatever it is i don't know the real circuit
and i also don't know what would be the output of a 3bit flash adc

would really appreciate some help
 

Aritra17

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what will be the output waveform
and what should i use in the generator part???
 

kalidasascreator

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Do post the link of your code, it will simplify the understanding!
 

Aritra17

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**comparator**

.subckt cmp in ref out Vdd Gnd
M1 Gnd ref N3 Gnd Nh L=.15u W=1u AD=66p PD=24u AS=66p PS=24u
M2 N3 ref bufr Gnd Nh L=.15u W=11u AD=66p PD=24u AS=66p PS=24u
M3 N2 in N3 Gnd Nh L=.15u W=11u AD=66p PD=24u AS=66p PS=24u
M4 N4 bufr Gnd Gnd Nh L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M5 OUT N4 Gnd Gnd Nh L=.15u W=.5u AD=66p PD=24u AS=66p PS=24u
M6 N4 bufr Vdd Vdd Ph L=.15u W=20u AD=66p PD=24u AS=66p PS=24u
M7 Vdd N2 N2 Vdd Ph L=.5u W=6u AD=66p PD=24u AS=66p PS=24u
M8 bufr N2 Vdd Vdd Ph L=.5u W=6u AD=66p PD=24u AS=66p PS=24u
M9 OUT N4 Vdd Vdd Ph L=.15u W=15u AD=66p PD=24u AS=66p PS=24u
.ends cmp


**resistor(.5)**

.subckt res in out
R1 in out 0.5 TC=0.0, 0.0
.ends res

**resistor(1)**

.subckt rest in out
R1 in out 1 TC=0.0, 0.0
.ends rest

**xor**

.subckt xor a b out Vdd Gnd
M1 abar a Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M2 bbar b Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M3 b abar bufr Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M4 bbar a bufr Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M5 N2 bufr Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M6 out N2 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M7 abar a Vdd Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M8 bbar b Vdd Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M9 b a bufr Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M10 bbar abar bufr Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M11 N2 bufr Vdd Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M12 out N2 Vdd Vdd Ph L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
.ends xor

**buffer**

.subckt buff a b Vdd Gnd
M1 N4 a Gnd Gnd Nh L=.15u W=2u AD=66p PD=24u AS=66p PS=24u
M2 b N4 Gnd Gnd Nh L=.15u W=.5u AD=66p PD=24u AS=66p PS=24u
M3 N4 a Vdd Vdd Ph L=.15u W=20u AD=66p PD=24u AS=66p PS=24u
M4 b N4 Vdd Vdd Ph L=.15u W=15u AD=66p PD=24u AS=66p PS=24u
.ends buff

**encoder**

.subckt enco d1 d2 d3 d4 d5 d6 d7 e3 e2 e1 Vdd Gnd
M1 buff1 d1 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M2 Gnd d2 buff2 Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M3 buff2 d3 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M4 buff1 d3 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M5 Gnd d4 buff3 Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M6 buff3 d5 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M7 buff3 d6 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M8 Gnd d7 buff3 Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M9 buff2 d6 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M10 Gnd d7 buff2 Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M11 buff1 d5 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M12 Gnd d7 buff1 Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M13 N1 buff2 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M14 e2 N1 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M15 N3 buff3 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M16 e3 N3 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M17 N4 buff1 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M18 e1 N4 Gnd Gnd Nh L=.15u W=.3u AD=66p PD=24u AS=66p PS=24u
M19 Vdd Gnd buff3 Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M20 Vdd Gnd buff2 Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M21 Vdd Gnd buff1 Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M22 N1 buff2 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M23 e2 N1 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M24 N3 buff3 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M25 e3 N3 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M26 N4 buff1 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
M27 e1 N4 Vdd Vdd Ph L=.15u W=.6u AD=66p PD=24u AS=66p PS=24u
.ends enco

**circuit**

**resistance ladder**

Xres_1 ref r1 res
Xrest_1 r1 r2 rest
Xrest_2 r2 r3 rest
Xrest_3 r3 r4 rest
Xrest_4 r4 r5 rest
Xrest_5 r5 r6 rest
Xrest_6 r6 r7 rest
Xres_2 r7 Gnd res

**comparator**

Xcmp_1 in r1 c1 Vdd Gnd cmp
Xcmp_2 in r2 c2 Vdd Gnd cmp
Xcmp_3 in r3 c3 Vdd Gnd cmp
Xcmp_4 in r4 c4 Vdd Gnd cmp
Xcmp_5 in r5 c5 Vdd Gnd cmp
Xcmp_6 in r6 c6 Vdd Gnd cmp
Xcmp_7 in r7 c7 Vdd Gnd cmp

**generator**

Xxor_1 Gnd c1 x1 Vdd Gnd xor
Xxor_2 c1 c2 x2 Vdd Gnd xor
Xxor_3 c2 c3 x3 Vdd Gnd xor
Xxor_4 c3 c4 x4 Vdd Gnd xor
Xxor_5 c4 c5 x5 Vdd Gnd xor
Xxor_6 c5 c6 x6 Vdd Gnd xor
Xxor_7 c6 c7 x7 Vdd Gnd xor

**encoder**

Xenco_1 x1 x2 x3 x4 x5 x6 x7 e3 e2 e1 Vdd Gnd enco

**buffer**

Xbuff_1 e1 b1 Vdd Gnd buff
Xbuff_2 e2 b2 Vdd Gnd buff
Xbuff_3 e3 b3 Vdd Gnd buff

**simulation**

v27 ref Gnd 3.0
v28 in Gnd sin 0 5.0 1000000 0.0 0.0 0.0
Vdd Vdd Gnd 5V
.dc v27 0 3.0 0.1
.tran 1n 1200n
.include dual.md
.power(Vdd)
.print v(in) v(ref) v(b3) v(b2) v(b1)
 

kalidasascreator

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Yes Aritra, I am Designing A Rf Mixer Circuit using Tanner T spice, But I couldn't find enough documentary about Tspice . i good at VHDL and Verilog ,
Can you assist me any way, i would be grateful.
Thank you.
 

Aritra17

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yaa sure

im good in vhdl too..............studied verilog a bit......bt nt good

what do you wish to design?????

send me the circuit diagram then i will see

you have to use s edit first then t spice
 

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