Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

3 and 4 terminal devices in cadence

Not open for further replies.


Member level 5
Oct 25, 2007
Reaction score
Trophy points
Activity points
in cadeence NCSU CDK, there are three terminal devices (NMOS and PMOS) and four terminal devices (NMOS4 and PMOS 4), by default, in three terminal devices, body is tied to gnd for nmos and vdd for pmos. if i use four terminal devices, and tie body of NMOS4 and PMOS4 to gnd and vdd respectively, is it equivalent to use the three terminal devices? hope someone can share your experience

It is equivalent from the libraries I have used. Haven't used NCSU CDK though but it should be simple enough to confirm by viewing the netlist.

ya it is true... it just serves better when you are gonna avoid body effect that is all... saves a little time....

to aryajur: how to confirm "viewing the netlist" ? could you show me?

In the Analog Artist Window there is a option to view the netlist. In the netlist you can see how each device is netlisted out and what model is it using, you can compare it for both and see if everything is the same or not.


    Points: 2
    Helpful Answer Positive Rating
Having four terminal for a device is because you have the chance to connect body other than VDD or VSS, by default, to avoid body effect when you cascode two devices or use it as input pair in OP-AMP. It is the SAME if you connect it back to VDD or VSS as the three terminal device. There is no need to check netlist and it's pretty sure


I originally use three terminal device, but when i replace them with 4 terminal device ( all sources of Nmos tie to gnd, and source of pmos tie to vdd), i did not get the same result (new one not working), that is why i ask such a question.

try simulating the characteristics of 3 and 4 terminal device separately in some amplifier configuration and maybe you would be able to know the difference and hence the cause of the deviation,,,....

i sim DC with nmos device, the result (DC current) is slightly different, please check the picture for schematic and netlist.


The only difference in the netlist is the gnd! node in one transistor. I am not sure how is gnd! connected to node 0. It should be the same, if it is there doesn't seem to be any reason why the DC characteristics are different. The thing to investigate is how and gnd! and 0 connected does the gnd symbol do that directly or is there something we don't know.

cadence takes some value for the resistance of the wire... try playing with it and see whether there is any change in the Id....

"takes some value for the resistance of the wire... try playing with it ", but how to?

i remember seein it in the properties table..... i dont remember the exact steps..... if i go to my college lab any of these days i'll post the exact steps.....

Not open for further replies.

Part and Inventory Search

Welcome to