0.35um sheet resistance
Can anyone help me understanding why 2nd poly is afterall needed? Also wht is the maximum w/l that can be drawn for this particular process? Pls also tell me wht is minimum w/l value acceptable.
Can anyone upload device formation document for TSMC 0.35u 2P4M process.
Thanx,
Hi Gold kiss,
The TSMC 0.35u 2P4M technology is actually modified from CMOS 1P4M salicide recently. The second poly is for PIP cap usuage. Also you can take it as a poly resistor. The HSR (high sheet-resistance resistor) is not supported in this technology, since there is no salicide or no-salicide difference either in poly1 or poly2 on this technology. If you ask why, I'd say this is originally a process for digital design. I don't think TSMC do put much effort on this technology for analog or RF purpose. If you're not sure how to draw the cap correctly, I suggest you to find the design rule for this technology. What I remember from the lvs file, cap is only defined in region POLY1 AND POLY2. As for poly2 resistor, I guess they're all salicide and you really don't have to think too much on drawing this layer. Just take it as a 50ohm-square resistor. Concerning the W/L ratio, you should notice first your supply voltage. Since the oxide thickness is different for 5V and 3.3V in this technology, don't use 5V devices if your supply won't exceed about 4V(for matching and speed issue). 20/0.35 and 0.4/20 should be allowed. The model for width lager than 20um is from math results, not fitting that well as those from 0.4~20um. Don't try to believe the simulation results if you use width lager than 20um. Though TSMC's manual could provide this value to 200um. Cliff