2nd flip-flop metastablity in reset synchronizer

[vijay82]

From one of the much vaunted Cliff Cumming papers on reset synchronization of async resets:

The second flip-flop of the reset synchronizer is not subject to recovery time metastability
because the input and output of the flip-flop are both low when reset is removed. There is no
logic differential between the input and output of the flip-flop so there is no chance that the
output would oscillate between two different logic values.

It says that because there is no logic differential (input and output are both 0) at the second flop, reset recovery violation will have no affect on its stability.

In a normal flip-flop, even if the input and output are same and setup time (similar to recovery time) is violated, the flop will go metastable. Is it in the nature/character of the reset recovery time that, given that input and output have same values, no metastability will occur if the time is violated? That is, is it a special case?

 

[FvM]

The statement is about the special case of "recovery time metastability" (related to asynchronous reset input), not claiming no FF metastabilty at all.

 

[vijay82]

I take it you're saying its a special case. Can you point to any references (other than this paper) which support the claim?