2D Convolution in verilog

[jiyaa]

how to implement 2d convolution in verilog, I have 3X3 kernel and 3x3 input signal and also how can I generate an input signal file in test bench to be read by readmemh command ???
thanks

 

[rca]

what is your goal? if you want to implement a 2D convolution in RTL code for ASIC or FPGA, the readmemh would not help you. that's not synthesisable.

 

[jiyaa]

what is your goal? if you want to implement a 2D convolution in RTL code for ASIC or FPGA, the readmemh would not help you. that's not synthesisable.

My goal is to implement a 2d convolution in RTL for FPGA but as i am new to verilog programming i dont have the idea how to enter the 72 bit of input data stream in the test bench? and how can i move my kernel origin over the other input pixel after calculating one??

 

[rca]

what should provide the 72 bits? a PC another microprocessor, through a memory?

 

[jiyaa]

what should provide the 72 bits? a PC another microprocessor, through a memory?

my input file is a hex file generated by matlab, now I need to input this file in verilog testbench

 

[jiyaa]

my input file is a hex file generated by matlab, now I need to input this file in verilog testbench

Can you please help me in thid regard, I have 7x7 input matrix and 3x3 kernel matrix for 2d convolution
thanks