sresam89
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Hi all,
I am stuck in a code part
please help
SAM
I am stuck in a code part
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 reg [3:0] memory[0:255]; ..... initial begin $readmemb("out.txt", memory,0,255);//this is reading fine end ..... always@(posedge clk) begin $display("%d\n",address); descriptor = $fopen("in.txt","w"); $fwrite(descriptor,"%b\n",memory[address]); //how do i write in here? [3X255] $display("%b : %b\n",address,memory[address][0:3]); //also display the same here #210 $fclose(descriptor); end
please help
SAM
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