Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

What limits an FPGAs speed?

Status
Not open for further replies.

TickleMonster

Newbie level 4
Joined
Feb 18, 2009
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,327
Hello,

Please bear with me as I know very little of FPGAs and the like, so I apologise if this is a fairly trivial question. :oops:

I'm curious, what is it that limits the clock frequency of an FPGA; traditional processors have been running at 3Ghz for quite a while now, but I'm unsure why FPGAs for all their power are not quite breaking the 1Ghz barrier?

Similarly, is it this speed issue that prevents an FPGA like the cyclone 3 for example taking full advantage of the speed of a DDR3 module such as the DDR3-2133?

And one last separate question if you don't mind; I notice some FPGAs can cost astronomical amounts (over £18,000), what place do they have in the industry and what would they be used for?

Thank you!
 

As far as I know...they are general purpose and must be programmed...They are programmable ASICs (kind of)...problem with fpga is the power comsumed..they take lot of power and area..FPGAs are used for prototyping in the industry...
 

Processors working at 3GHz are fully optimized. They are designed using ASIC approach. Timing paths are fully optimized in ASIC. Maximum operating frequency of a circuit is determined by the slowest path in the circuit. This depends on the transistor switching and net delay. Transistor switching means how fast a transistor can switch ON/OFF. Net delay is the routing delay. With the transistor scaling switching speed of transistor is increasing but the limiting factor is net delay. In a processor working at 3GHZ timing paths are fixed and optimized while FPGA timing path changes with programming. They are general purpose. Timing paths are not optimized.

They are general purpose and programmable so the require large chip area. They also uses different technology than ASIC for fabrication. Hence costly.

USES:

1. FPGAs are mainly used for product prototyping. The cost of ASIC development is very high. So initially product are prototyped using FPGA and if there is a good market they can go ASIC. Ofcourse performance is not as good as an ASIC.

2. Time to market is less for product. You just need to dump a bit file (FPGA programming file) to get desired functionality. It is matter of hours. While ASIC requires months to design and fabricate.

3. You can test your design performance in real hardware.
 
Also, remember FPGAs are not processors - they are anything you want them to be.

FPGAs have up to around 1000 IOs (depending on part), so if you wanted you could have a 999 bit data bus in, and single bit data bus out. They can also process huge volumes of data compared to a processor because it is all processed in parrallel. You can easily take in, process and then output several video channels in parrallel.

So it is very unfair to compaire 3GHz processors to FPGAs. but I bet for some fixed point algorithm with little decision making an FPGA running at 100MHz could out perform some 3GHz processors
 

My apologies for not replying sooner, thank you all very much for the detailed responses.

So, if the maximum operating frequency of the FPGA is dependant on the transistor switching speed, then do the transistors in ASICs have a much higher transistor switching speed than those in FPGAs? If so, why is this?

Thanks once again.
 

The transistors themselves would be capable of fast switching speed, because FPGA's are typically implemented on the same cutting-edge processes as CPU's. The issue is that for any useful work to be done, the outputs from one gate/FF have to connect to the next gate/FF. I believe a lot of the resources on an FPGA are dedicated to purely routing instead of logic. So, the limitations come from connecting all the logic together since it must be flexible.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top