ASIC Design Methodologies & Tools (Digital)

[nagssmiles]

how to write program in primetime.mow i am having the vhdl code.from that code how to write prime time code for finding power dissipation & delay

 

[phoenixpavan]

Hello again Nag,

Prime time is a tool to do timing analysis for your design....you cannot directly take your vhdl code to primetime. There are several steps before you reach timing analysis.Let me get you through a full asic design flow

After writing your HDL code(VHDL/Verilog) you need to perform your verification which is checking your design for functional correctness. Once your design passes verification you need to do Synthesis using Design Compiler which is nothing but translation+optimization+mapping of your design to particular technology (65nm,45nm etc) using sdc file along with libraries and wire load models which contain cell and net dealys. These will help you to perform initial timing analysis but not the last. After synthesis you do physical implementation steps(placement--cts--routing) using IC compiler. If it is a hierarchal design we do partitioning as well. Now we will take our design to Primetime for timing closure where we will have the exact net delays which are extracted after routing. You should give netlist as input for primetime. Primetime can also be used for timing analysis after every step in design flow because anyway all the tools inherently does timing analysis to a particular extent but primetime is considered as sign-off for timing.Primetime will do the analysis using tool commands. This command flow can be automated using scripts which can be written using Tcl. There are still several steps in the design but that would be easy to find out for you now..

Power analysis will be done by tools such as powerrail etc..not primetime

Hope you now get a clear picture....Helpful??

---------- Post added at 23:14 ---------- Previous post was at 23:03 ----------

please change the title of your thread from next time...it need not be the forum name.

 

[nagssmiles]

thank u sirrrrrrrrrr. the information which u hav given is helpful.what is the next step i hav to do after having my vhdl code. whether there is any different coding style for prime time or can it be generated from the vhdl code itself.....pls give me commands if so......plsss plsss sir its very urgent.....

 

[phoenixpavan]

Once you are through with your vhdl, please verify your design with a testbench and if the functionality is correct then everything follows........

I strongly suggest you to go through this entire pdf
userwww.sfsu.edu/.../synopsys%20tutorials/ASIC%20Design%20Flow%20Tutorial.pdf - United States

Do not neglect reading the pdf because only then you will understand when to use PT and how to use it clearly...

 

[nagssmiles]

sorry sir......the link u sent is unable to get connected.......it is dispalying as page is not found

---------- Post added at 08:40 ---------- Previous post was at 08:37 ----------

i hav simulated my code using test bench & it is working properly and i am getting the correct outputs......now i need to find power dissipation& delay of that circuit using primetime tool.or is there any other way to find them at gate level logic

 

[phoenixpavan]

If you just need to generate timing report may be you should just use Design compiler.The procedure will be in detail in the userguide

dc_user_guide from https://www.edaboard.com/threads/12589/

Similarly if you still want to use Primrtime, the commands and all the info will be in userguide from this thread
Primetime userguide:


About the previous pdf just google for Asic Design flow tutorial using Synopsys tools, the first hit is the pdf you are looking for