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200MHz DDR Memory controller

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mami_hacky

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specctra sdram pcb

Who has designed any controller for these devices? I have to design one. Timings are really tight. There are many points that should be considered.
Any idea or help?
 

tanuki

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ddr memory design

Fairchild, Intersil and Maxim (and others) all have execelent circuits and applications notes for DDR memory systems SMPS.

Via Technoligies has a good resource page: www.via.com.tw/jsp/en/products/ddr.jsp
 

kinysh

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memory controller read operation

even sdram can run faster than 100Mhz. my sdram controller can run that too without dll.

200M DDR is not so faster. only when trans data it use two edge.
using dll that should be really easy.
the clock is only 100M
 

mami_hacky

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200mhz virtex-ii

The clock frequency is 200MHZ, dus allowing 400Mbit/s/pin data transfer.
 

kinysh

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a simple memory controller design

This is something.
you should really deal it with a dll.

acutally my next job will very perhaps be designing a DDR sdram controller.
so, if you have some info and some design , can you share it with me?
 

mami_hacky

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route pcb with ddr memories

Clock DLL? OK! it is an essential part. In addition, a signal integrity check is completely essential. timing constraints for the controller will not be as eeasy as normal designs.
Any how, the new product from ATi, RADEON 9700, graphics card, uses a 256 bit width data bus, which connects the cpu to the DDR memories, running in 310MHz, clock frequency. the total bandwidth is 20Gbits/s. I really wonder how they have done this.
 

kinysh

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memory at over 200mhz

200Mhz is not too difficult for .18 process.
our design can run 150Mhz at worse case in .18 without code change.

however for 300Mhz that is something difficult, should be careful when designing.

and I think when they say 300Mhz they mean 300Mhz typical case, for worse case it may run 2XX.
 

igorsat

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memory controller design

I designed a DDR SDRAM controller that works at 235MHz in Virtex-II XC2V1000, speed grade -4. Designing a controller in ASIC is a little easier, because the logic runs about 3-5 times faster at the same process (0.15um for Virtex-II). I mean if DDR controller in Virtex II runs at 200MHz, then theoretically it should run at min. freq. of 600MHz in ASIC. If you want to reach high working freq. you will have to pipeline the design, carefully balance the output fan of speed critical logic and don’t rely on synthesis tools too much. If you are going to design a “smart” controller that will be able to:
•Figure out if the current write/read operation is performed on an already opened bank/row.
•Rearrange write/read operations in a way that minimum number of row/bank bank precharges are needed.
•Figure out, when the next refresh cycles will be needed and adjust that with next read/write operations…
If the above is true, then the max. freq. of controller will be at least 30% lower.
You can find many DDR related documents on xilinx’s web site. Are you going to design a controller that will be connected to single DDR chip (point to point connection) or will be connected to DIMM module(s)?
Designing a PCB is also a little tricky at such high freq. (crosstalk, EMI, ground-bounce…). You will definitely need a signal integrity tool like hyperlynx. And of course you will have to use DLL to adjust the phase of read/write clock, because you will need to adjust the sampling point (read) to maximize the data-eye and to output the data at the correct point (write). How wide is your data bus going to be? 64, 128bits? If that is the case then you will need many large decoupling capacitors near the ASIC/Xilinx.
 

mami_hacky

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pll in ddr controller

Very Very thanks, for your good answer,
The clock frquency for the design, I think will not be a problem for me, since I now how to optimize my design logic to achive high clock freqs.
It has been my work for many years.
But, the point, which I'm really afraid of, is the read/write operation from/to ddr module. I'm using a point to point connection, and I'm afraid of these very little data valid windows. suppose that you have only 1.5 ns time to capture your data. a simple mistake, will destroy every thing.

May I ask, if you have tested your design in practice? I think 200MHz clock frequency is something really high, for a virtex-II FPGA, then I wonder how, you have done this work using a -4 speed grade.
Will the Virtex-II's digital clock manager, operate normally under these high clock frequencies? and will it be able to shift the signal, correctly. as you know, even a little mistake will...
Finally I have to use 4 DCMs for the design, which may make some problems.

Xilinx provides an app note on designsing a 200MHz ddr interface, but I don't know if it is really possile in practice.
 

roli

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ddr memory fanout

The key for a 300Mhz DDR memory PCB system design is:
1. Having strict control on PCB delays (a good PCB tool such as Specctra can do the job for) - with the goal the tightly Minimize & Control the Clock Skew - between DDR Controller, Memories, and CPU (busses).
2. Having a PLL in each design - to minimize the Skews inside Chips/ASICs, and Bus interface units.

Can someone elaborate (or give eBooks info) for DLL design ?
 

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dqs shift ddr

DDR timings at such high frequencies are really very tight, so you have to replicate logic all by yourself. Don’t allow synplicity or any other synthesis tool to do that for you. You have to fix IOBs, RAMBLOCKs, and DCMs, constrain critical logic to predefined location on chip. There aren’t any outputs in my design with fanout higher than 8. Aligning DQS with clock signals and data signals in the middle during the write operation is not so problematic if the output FFs are located in IOBs and all IOBs are of the same type. The problem is read operation. I found out that if I sample the input clock DQS during the read operation and phase shift this clock. I can’t always reliably retrieve the data, because the data eye shifts depending on the Xilinx and DDR temperature. Instead I must find out the correct sampling/read frequency by writing a block of data and then I try to read from this location. I set the starting read clock phase to 0 and repeat the read for each phase. This way I can find the maximum data-eye and position the phase in the middle of data-eye. I need to recalibrate the phase each time the temperature of xilinx exceeds the predefined limit. If you can’t afford to do that, you will have to try the standard approach. At the beginning I relied too much on synthesis tools and the max. frequency I was able to achieve was 120MHz. I’m using 7 DCMs in my design and 87% of the xilinx is filled and DDR controller is using about 20% of that space, but I using only 4 different clocks in each quadrant. I tried the app note but I wasn’t able to achieve 200MHz only about 152MHz in the same chip. I’m using 10 layer PCB and without signal integrity tools I wouldn’t be able to revive the design. There aren’t any P/R tools (specctra included), which can replace human brain. I did place and route the PCB all by myself. This way the maximum crosstalk I have on data lines is only 65mV and the number of vias is minimal. Don’t forget to use maximum of three vias per data line, well that depends how long you data lines will be but less vias the better.
 

mami_hacky

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dll ddr controller

Very Great answer, I really appreciate your work
So, you say Xilinx's device is capable of doing this.
Thanks for answer.
 

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