[SOLVED] 2 Stage Op-Amp Stability Analysis

[Shady Ahmed]

I ran the same simulation parameters as u said, it is really weird results that i don't get, now , vcmf doesn't saturate, it swings between 500 mv & 633 mv.

However, vo_1_r & vo_1_l swings between 1.19 v (almost Vdd) & 800 mV !! which causes the 2nd stage output to saturate also, does that mean that stage 1 is unstable ?! if yes, how can i make sure it is !

 

[FvM]

Your latest simulation show the amplifier in overload, input differential voltage is much to high, in so far the results are meaningless for regular operation. Please repeat with reasonable parameters, resulting in non-distorted output.

 

[t4_v]

No, no. Everything is now fine if you're using testbench here: . However, I see that you apply your inputs through something, because you have: Vin_src and Vin.


Now run the second testbench where opamp has feedback loops as we discussed previously:

https://www.linear.com/product/LTC1992 .
Your input signal will be 0V +/- 1.2 V and outputs should be 0.6 V +/- 0.6 V.
However, firstly I would not check rail-to-rail operation. Let's try for example 0V +/- 0.6 V as input signal and the outputs should be 0.6 V +/- 0.3 V.

 

[Shady Ahmed]

No, no. Everything is now fine if you're using testbench here: .

No, the last simulation was for the integrator as u mentioned here :

Please, use much lower input signal frequency (now we have 10 MHz), for example 1 kHz. Additionally, introduce a delay time for the input signal. The delay may be 3 * period. For example:
- f_in = 1 kHz
- delay = 3 ms
- simulation time = 6 ms

Now, i ran a unity gain test bench as shown in the schematic:



and the output has distortion due to saturation also




and here is the op-amp schematic for net names

Your latest simulation show the amplifier in overload, input differential voltage is much to high

Yes, it is clearly overloaded ! but why ?! see for instance the unity gain test bench in that reply, the i/p amplitude is only 0.1v. and the open loop op-amp analysis shows that it is stable! why did the test bench saturate??!

Thanks for your help

 

[FvM]

and the output has distortion due to saturation also

There's no distortion in the output voltage, just a certain distortion at first stage output which is apparently corrected by the feedback circuit and respective loop gain.

So the circuit is basically working. If the transistor areas and other parameters can be further optimized is a different question.

 

[t4_v]

Nice job.

The outputs of the first stage can saturate. This is not a problem. It is important how the outputs Vo- and Vo+ behave and they behave correctly.

Finally, everything seems to behave as we can expect.

If you could, pleas construct the testbench I mentioned in the last post and we will see how the opamp behave.

 

[Shady Ahmed]

So the circuit is basically working

The next figure shows the output with the same test bench , but with 1 Mega Ohm as feedback and source resistors,
why the output range is from 437mV to 630mv instead of exactly following the input wave ? would that be harmefull in the system and how can i fix it?

If you could, please construct the testbench I mentioned in the last post and we will see how the opamp behave.

Here they are:
it seems to be working fine too, but with the same offset problem , right?






Thank you both.

 

[t4_v]

Nice job.

Now, the circuit is "stabilized" and behave as we expect it to behave. Congratulations!

Yes, it seems that the opamp has an offset.
Vin = 0.6 V +/- 0.1 V
Vo = 534 mV +/- 48 mV

I calculated 534 mV. Because you showed a specific x-range there is not data on your plot regarding the time where there is no AC input signal. So it looks like there is 0.534 V on both outputs Vo- and Vo+ when input signals (Vin+ and Vin-) are equal to 0.6 V.

So please tell what are your concerns now? What would you like to achieve?

 

[Shady Ahmed]

I am trying to use the op-amp as an integrator, the coefficient of my integrator would be : R*C = 44n ...

So for instance ,i chose R = 44K & Cap = 1p.. the input is a sine wave and of course, the output is expected to be a cosine wave

The schematic:



However, the output is clipped as u can see in the following output plots.




So, is that from the value of R & C or is the test bench wrong somehow?

 

[FvM]

So, is that from the value of R & C or is the test bench wrong somehow?

Either too small integration time constant or too large input signal.

 

[t4_v]

I am not sure if the differential integrator would work as you expect it to work, because I do not have experience with differential opamps working as integrators. Normally when you use opamp working as an integrator like here:

http://ecetutorials.com/wp-content/uploads/2014/01/Opamp_integrator1.gif

the opamp knows the the Vin- should stay at ground due to the fact that Vin+ is grounded.

In your circuit both inputs Vin+ and Vin- are used.


However, we can try.

Firstly, please do not increase input signal frequency. 1 kHz is ok. We know that for this frequency your circuit works correctly.
Secondly, when you show plots please, show also the time when everything is DC. You can decrease the delay time to 1 ms and run your simulation from 0 to 4 ms to have 3 periods of input signal.
Thirdly, put 1 Meg resistors in parallel to capacitors.

 

[FvM]

I am not sure if the differential integrator would work as you expect it to work, because I do not have experience with differential opamps working as integrators.

You already mentioned this in post #9 and Shady Ahmed assured you that the topology is pretty standard, which can be confirmed. In case of doubt you should try a circuit analysis which shows that the differential integrator is just a symmetrical completion of the standard single ended configuration. Similarly, you can convert many single ended OP circuits to a fully differential variant.

Thirdly, put 1 Meg resistors in parallel to capacitors.

Could be necessary if the circuit doesn't achieve a suitable operation without it. In a simulation, the integrator operation point can be also achieved by setting initial conditions. DC bias isn't yet a problem in the present simulation.

You can calculate the integrator gain for 10 kHz (assuming an "ideal" high gain amplifier). It's about 360, so no surprize to see it overloaded with 100 mV input.

 

[t4_v]

Ok, I had time to analyse the differential integrator. I agree, it works.

Yes, 1 Meg resistor is just to have zero voltage across capacitor and it can be also done using initial conditions.

And the problem of saturated outputs here:


for the testbench here:


can be solved by either lowering input signal values, as you mentioned, or by increasing R33 and R34 values or by increasing C1 and C2 values.

 

[Shady Ahmed]

First of all , thank you both very much, i appreciate it.

Now , i used the integrator test bench, with the following parameters:
R= 44k , C= 0.036p & Fin = 100 MHz ,, which using the relation : Gain = 1/(R*C* omega)
the gain should be = 1

The following is the simulation output





The output signal amplitude is 150 mV instead of 200 mV

I guess that can be tolerated due to non idealities, right?

However, what about the offset? The output common mode is around 540 mV instead of 600 mV (as appears in the second image). Will that affect my Sigma Delta ADC performance? how can i correct that ?

 

[FvM]

I presume, you can show that the results are expectable due to the finite gain of the main and CMFB amplifier.

Small common mode offsets shouldn't affect the operation of a true differential circuit, e.g. a SD modulator, CMFB is only there to keep the DC voltage level within the linear range.

 

[t4_v]

Fin is 100 MHz now. Attenuation may appear for high frequencies. For 1 kHz input signal in the testbench:



we had quite good results:

Vin = 0.6 V +/- 0.1 V
Vo = 534 mV +/- 48 mV

gain vs frequency plot could tell what is expected for given frequencies.



Regarding offset, your CMFB gain is set to 10 V/V (). If you increase this gain your outputs will be close to the ideal 600 mV.