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2 stage op amp slew rate

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coolsummer

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In the book Analog Design Essentials, the author says that "This SR appears at the output as the VGS6 is still about constant. Indeed, transistor M6 still conducts as if nothing has happened!" But,why? Since M4 is on, the voltage of Node 1 will ultimately become low, so M6 would turn off and make Vout a high voltage. How can M6 still conduct?
 

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You can think of M6 as a lousy integrator while the circuit is slewing. The current from the first stage will go through the compensation cap. Of course, Vgs of M6 will change a bit but approximately we can consider it as constant with respect to the much bigger variation of the output (drain) of M6. So, the rate of change in the output will be defined by the change of voltage across the cap as it has been charged by a constant current. Once the output reaches Vdd, of course everything breaks. Vout can't go up any further but the capacitor still has current and now there is no other way but gate of M6 to start decreasing until the transistor is off.
 

You can think of M6 as a lousy integrator while the circuit is slewing. The current from the first stage will go through the compensation cap. Of course, Vgs of M6 will change a bit but approximately we can consider it as constant with respect to the much bigger variation of the output (drain) of M6. So, the rate of change in the output will be defined by the change of voltage across the cap as it has been charged by a constant current. Once the output reaches Vdd, of course everything breaks. Vout can't go up any further but the capacitor still has current and now there is no other way but gate of M6 to start decreasing until the transistor is off.
But since current IB is flowing from the plate of Cc which connects to Node 1, the other plate of Cc(i.e, Vout), has no charge accumulation, how can Vout rise up to Vdd?
 

Hi,

The capacitor current is : I_c = C × V / t ...
It means the current is proportional to "voltage per time". And voltage per time is identical to slew rate SR.

Klaus
 

But since current IB is flowing from the plate of Cc which connects to Node 1, the other plate of Cc(i.e, Vout), has no charge accumulation, how can Vout rise up to Vdd?


What do you mean the other plate doesn't charge? If there is charge accumulating on one plate, an opposite in polarity charge accumulates on the other plate. It's just physics.
 

What do you mean the other plate doesn't charge? If there is charge accumulating on one plate, an opposite in polarity charge accumulates on the other plate. It's just physics.
yeah, an opposite in polarity charge accumulates on the other plate, so there's current flowing into the other plate, but where does this current(Ib') come from?
 

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From M5 and discharging CL
well, I'm still confused about the current Ib'. (1). If Ib' is from M5, does it mean that the current of M5 will be larger than that of M6? (not equal?) (2). If Ib' is from discharging CL, it means that the charge moves from the upper plate of CL to the right plate of Cc, but they are just one node (Node 4), the net charge on Node 4 doesn't change, how can Vout rise up?
 

The current that goes through the capacitor is equal to the tail current of the diff pair i.e. the current in M7. Current in M5 is B times higher as per the drawing. Slewing is a non linear process. So, 1 part of the current from M5 goes into the capacitor Cc, the rest is distributed between M6 and the load cap+load resistor. The way it is distributed depends on the value of Cc because the drain voltage of M6 changes as Ib'/Cc, roughly speaking. M6 drain voltage increases, so correspondingly the voltage of CL has to increase, because as you said CL and Cc connect at the same node. We assume that the Vgs of M6 stays more or less constant as in a high gain integrator. But it is not a high gain integrator, so it also changes to allow M6 to take the portion of the current of M5 that's not going into Cc (and the load). But that change is much smaller than the change in the drain voltage.
 
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