In my project i have my own vhdl code and also i am using a microblaze , now i implemented my vhdl code next to microblaze in the same vhdl top file , now microblaze clock input is directly from oscillator pin which is a 200MHZ clock and for my vhdl code i need a 100MHZ clock , so how from my 1 clock oscillator i can generate diffrent clock signals with different frequencies ?
Yes, that is the standard way of generatin and distributing many clocks from a single clock input in an FPGA. Open coregen and search for DCM (Digital Clock Manager). There will be a link to the datasheet.