2 questions about VHDL language

[hawking1122]

2 questions about VHDL

Hi, I'm trying to write code for a D type flip flop. Then, there are 2 questions coming up in my mind. Let's first have a look at the code:

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port
(
d,clk,rst: in std_logic;
q: out std_logic
);
end dff;

architecture behavior of dff is
begin
process(clk)
begin
if(rst='1') then
q <= '0';
elsif (clk'event and clk='1') then
q <= d;
end if;
end process;
end behavior;

My 1st question is: The code above works well. But if I replace the code line: elsif (clk'event and clk='1') then with this line:[/b] elsif (clk='1') then[/b], the result will be different. In my opinion, it is apparent that process code block will be executed every time [/b] clk[/b] is changed so we don't need to add [/b]clk'event[/b] inside that code block. Can you explain it for me?

My 2nd question is: What does a variable represent in real electronic circuit. Or more clearly, what would happen with my hardware if I state a new variable? What is the benefit I have if I use a signal instead of a variable?

Your help would be great to me!

 

[raghava]

Re: 2 questions about VHDL

Hi,

Question1: if(clk'event and clk = '1') means rising_edge(clk) means the process block is executed wnever there is rising edge of clk is identified. More detail, clk'even mans changing clk from high to low or low to high. If you mention clk'even and clk = '1' means clk changing from low to high, which meant rising_edge(clk).
Since flip flops are edge triggered, you have to mention either if(clk'even and clk = '1') or rising_edge(clk).
Results would be different with simple if(clk = '1') which means process will be executed throughout the [period when clk = 1 which is called level triggering flip flop.

Question 2: A variable represents a 'wire' or combinational circuit output.
A signal represents sequential logic output. A variable can not store data and signal does it.
Variable analogies to wire in verilog and signal to reg.

Hope I helped you.

Regards

 

[dmk]

Re: 2 questions about VHDL

Question 2: A variable represents a 'wire' or combinational circuit output.
A signal represents sequential logic output. A variable can not store data and signal does it.
Variable analogies to wire in verilog and signal to reg.

In my opinnion this is not correct. A signal results in a sequential or combinational logic, depending on the situation - parallel or sequantial assignment. A variable is acceptable only inside process and it could result again in sequantial/combinational logic. The main difference between signal and variable is that the assignment of variable takes place instantly and you can use its new value on the next statement, while signal will change its value at the very end of the process.

 

[amraldo]

Re: 2 questions about VHDL

A variable can map to a wire or latch or a FF depending on its usage.
--
Amr Ali

 

[jardila]

Hi,

To avoid confusion, we must have this clear:

A signal represents a wire in the circuit, while a variable is not a physical element. This last one is only used in a process block and help us to execute any code that it requires.

 

[amraldo]

Referring to VHDL synthesis primer, a variable or a signal will map to a memory when any of the following 3 conditions is applicable:
1. assigned before used
2. assigned under certain conditions
3. needs to retain its value between different simulation runs

otherwise, the result will be a wire
--
Amr Ali

 

[lahrach]

variable is not synthetizable