2 Dimentional Input/Output Port in Verilog

[omara007]

Is it possible to have a 2-D Input (or Output) port declaration in Verilog ?

 

[sree205]

To my knowledge, it doesn't support two dimensional ports. Its possible to declare ports only as vectors, where the size defines the width of the data bus.

I hope that you are referring to the width and depth as two dimensions of the input/output ports.

 

[dreamscome]

It is one of the limitations of Verilog...

 

[sanjay11]

not in verilog, but think supported in system verilog using interfaces.

 

[michael_chen]

i may be support in verilog-2001

 

[FvM]

i may be support in verilog-2001

No, neither in Verilog 2005. But System Verilog 2005 introduces a type definition, that can be referenced in module ports. It should allow multidimensional arrays as well as structures in ports.