library ieee;
use ieee.std_logic_1164.all;
entity two_bit_counter_FSM is
port(clk,reset,load:in std_logic;count:out std_logic_vector(1 downto 0));
end two_bit_counter_FSM;
architecture arc of two_bit_counter_FSM is
type state is (s0,s1,s2,s3);
signal ps,ns:state;
begin
process(clk,reset)
begin
if(reset='1') then
ps<=s0;
elsif(clk'event and clk='1')then
ps<=ns;
end if;
end process;
process(ps,load)
begin
if(clk'event and clk='1')then
case(ps)is
when s0 =>
if (load='1') then ns <=s1; else ns<=s0;
end if;
when s1 =>
if (load='1') then ns <=s2; else ns<=s0;
end if;
when s2 =>
if (load='1') then ns <=s3; else ns<=s1;
end if;
when s3 =>
if (load='1') then ns <=s0; else ns<=s2;
end if;
end case;
end if;
end process;
process(ps,load)
begin
if(clk'event and clk='1')then
case(ps)is
when s0 =>
if (load='1') then count <="01"; else count<="00";
end if;
when s1 =>
if (load='1') then count <="10"; else count<="01";
end if;
when s2 =>
if (load='1') then count <="11"; else count<="10";
end if;
when s3 =>
if (load='1') then count <="00"; else count<="10";
end if;
end case;
end if;
end process;
end arc;