2.5V or 3.6V? for TDC application

[pralay.p]

My application is for Smart Water meter.
The TDC-IC I'm using is MAX35103 https://datasheets.maximintegrated.com/en/ds/MAX35103.pdf. My device is battery powered and operating at 2.5V .Which is regulated down using TPS62740https://www.ti.com/lit/ds/symlink/t...13017&ref_url=https%3A%2F%2Fwww.google.com%2F from 3.6V(battery voltage).
The application is current sensitive since being battery operated hence, using a DC-DC such as TPS62740.
Current requirement of the board: 200uA-50mA(min-max)

my questions are as below:

1. Will the power consumption of my board increase if I operate at 3.6 given directly from the battery(all the components on board are rated for 3.6 or above)?
2. What could be the alternative for DC-DC which has low o/p ripple noise that won't interfere with the TDC?
3. What techniques can be used to reduce the output ripples on the DC-DC and up to what extent?

 

[KlausST]

Hi,

Why not use 3V battery without regulator?

1) with increasing supply voltage it is more likely that the current also increases.
Since P = V × I ..... you have to expect higher power at higger voltage.

2) linear regulator, no regulator at all

3) passive low pass filters, linear LDOs. .. down to almost every noise level you want. It's a question of effort, cost, power consumption...

TDS has limited measurement range in time. It usually is used in time_of_flight applications. Electrical, optical or low distance acoustic applications.
In all cases you need to generate pulses. They need some amount of power, too. It's not mentioned in your post, nor is processin by a microcontroller mentioned. Be sure to focus on the part that consumes most power for your optimisation.
I neither think TDS nor the SMPS is the most power consuming part. Just guessing...

Klaus

 

[dick_freebird]

Question the power draw and its conditions. A
classical POL DC-DC is probably way inefficient
at 200uA load. 50mA may be a very infrequent
condition - what?

You could consider a fixed-ratio DC-DC rather
than a full featured chip. Suppose that you had
a 2/3 duty cycle made from CMOS logic; 3.6V
becomes 2.4V (3.3 becomes 2.2). For this use
do you need super accuracy and stability? Maybe,
maybe not. I think you could make a 2/3 DC-DC
from a quad NAND (phase shift osc and feedback
logic) and a dual DFF (2 bits for 00, 01, 10, 00, ...).

Couple of LC filter stages should be adequate to
knock down the ripple. Make the final filter have
a high C to ride out any short term high current
intervals lowering the demands on peak CMOS
output current. You could gang a hex inverter
or an octal bus driver for more current if need be.