1gsample/s double sampled sample and hold circuit

[platforma]

hi ,
I need sample and hold topology for my 6bit 1gsample /s adc.
any suggestion?

 

[erikl]

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You know this one?

 

[platforma]

which one?

 

[erikl]

which one?

I had uploaded an IEEE paper from Christoph Sandner et al.: "A 6-bit 1.2GS/s Low-Power Flash-ADC in 0.13µm Digital CMOS" IEEE JSSC, Vol. 40, 7, JULY 2005 , but it has been removed by Edaboard Admin (IEEE paper uploading isn't allowed).
Sorry, you were too slow :-(

 

[platforma]

hi ,thanks for answer. I looked at this paper. first of all my tech is 0.18tsmc and this i 0.13um. So probably I will not reach this speed at 0.18tsmc. and other and big issue is that , this paper is using ref voltage and input voltage together. but My adc is ready and I just need sample and hold circuit. and I must use just vin+ vin-. my reference voltages are after sample and hold block and inputs of preamplifier.

Added after 22 minutes:

I tried this topology but I have offset problem . these opamps are working 500Mhz but they have offset such as 4-5mV. but I have 20mV range for every step. 2^6=64 step . so 4mV is large for me when I decreased offset I have settling problem. I didnt find any opamp with low offset and high speed at 0.18tsmc . any suggestion for high speed and low offset opamp . or a new topology.

 

[erikl]

I tried this topology but I have offset problem . these opamps are working 500Mhz but they have offset such as 4-5mV. but I have 20mV range for every step. 2^6=64 step . so 4mV is large for me when I decreased offset I have settling problem. I didnt find any opamp with low offset and high speed at 0.18tsmc . any suggestion for high speed and low offset opamp . or a new topology.

Lower offset means larger input FETs and hence lower fT.

For other topologies s. e.g. these papers:
Michael Choi and Asad A. Abidi: "A 6-b 1.3-Gsample/s A/D Converter in 0.35-µm CMOS"
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001

Peter C. S. Scholtens, Member and Maarten Vertregt: "A 6-b 1.6-Gsample/s Flash ADC in 0.18-µm CMOS Using Averaging Termination"
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 12, DECEMBER 2002

Xicheng Jiang, Zhengyu Wang, M. Frank Chang: "A 2GS/s 6b ADC in 0.18μm CMOS"
ISSCC 2003 / SESSION 18 / NYQUIST A/D CONVERTERS / PAPER 18.3
2003 IEEE International Solid-State Circuits Conference 0-7803-7707-9/03

Xicheng Jiang and Mau-Chung Frank Chang: "A 1-GHz Signal Bandwidth 6-bit CMOS ADC With Power-Efficient Averaging" (0.18µm)
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 2, FEBRUARY 2005