1fst stage of op amp, diff pair question

[denismos]

Hi to all!

This my fisrt post!
I got a problem with the specifications of an op-amp. I think i dont understand basic stuff. I should design an op-amp (my first attempt!) with vdd=3V and

1. gain about 4000 (>70db)
2. Common mode range 0.5-2.5V
3. Output 0.5-2.5V

I picked the Miller amp as implementation (with Nmos as diff pair and Pmos Mirror as Current load). Tech is ami06. My question is kind of silly (prepare those vegetables), but I got stock. It has more to do with the specification:
I cannot make any sense on how much the input voltages must be. The diff pair doesn't function properly if the input voltages are large. In Bakers book it is mentioned that the pair currents cant be large so that the MOST function in sat. Needles to say that all MOST of the amp should be in sat. Whats the input voltages (10^verysmall volts???)? Can anybody help me clarify this?

Thank you in advance.

 

[atripathi]

input voltage range are typically <= supply voltage. So for your case it should be ~3V.

 

[rajanarender_suram]

Common mode range spec is what ur input valtage can be

 

[jimito13]

denismos,

There are no silly questions.Well,at first let's clarify what is small signal and what is large signal models :

(From Wikipedia)

A small signal model takes a circuit and based on an operating point (bias) it linearizes all the components. Nothing changes because the assumption is that the signal is so small that the operating point (gain, capacitance etc) doesn't change.

A large signal model on the other hand takes into account the fact that the large signal actually affects the operating point and takes into account that elements are non-linear and that circuits can be limited by power supply values. A small signal model ignores supply values.

For the case of your opamp large signal model comes from DC analysis and small signal model comes from AC analysis.You can say in simple words that all the DC voltages generated by the bias network and the power supply in your design are large signal and the signal that you inject in your opamp inputs is the small signal.As the definition of those two terms implies for their magnitudes always small signal<<large signal.Now let's define this << :

A small signal in the context of small signal analysis relates to the linear approximation of a transistor model around it's operating point. In the presence of a small signal the output is a replica of the input except for a change in amplitude. In simple terms this means that a sine wave in gives you a sine wave out.

A large signal will however make the device operate in a non-linear fashion by clipping the output or introducing various kinds of distortion.

So,if you feed your opamp (with gain 70dB as your specs say) with let's say 2V amplitude of sinus low-freq. signal (on top of the bias) then the output will be so big and>>3V(Vdd) that will be clipped or distorted.

If you take a look at Gray-Meyer's book at Chapter 1,pages 90-91-92 (Greek Version),it shows the small-signal model of transistors and gives an equation for when we assume a signal is small.I think it worths to take a look and see the analysis,you will get a lot.

If you want to speak with numbers...generally the signal at the input of your opamp will be at the order of mV or uV.When you start a design you must always be given the input signal (that your circuit must deal with at it's inputs-peak,rms,single or differential) in dBm or in Volts along with an impedance level.

I hope the above clarified your question.

 

[sapna.dudani@gmail.com]

**broken link removed**
try this link........

 

[vleam13]

use nmos for your differential pair so that you can make input range very close to supply.
(pmos closer to ground)

 

[sutapanaki]

Ok, let's get more focused on your needs. With the technology, supply and specs you have, your main problem is with the input common mode voltage. For the input stage you've chosen, when the input CM voltage is 0.5, you'll most probably put the tail current source into ohmic region which will reduce the tail current and worsen the common-mode rejection. On the opposite end, when your CM voltage is 2.5V, since you have PMOS current mirror as a load, you'll put in ohmic region the input NMOS transistor on the side of the diode connected PMOS transistor of the load mirror. I think you have at least two option to deal with the input common-mode range. Either use a folded cascode amplifier with NMOS inputs and with considerable effort maybe you can make the tail NMOS device big enough and also the diff pair devices big enough so that you still keep the NMOS tail in saturation - don't forget to connect the bulks of the nmos diff pair devices to their source if you can. Or you can use a configuration with two diff pairs, one NMOS, the other PMOS, working in parallel. This can also be done within the folded cascode topology.
As to the input voltages, they have to be somewhere within you input common-mode voltage range - this is when we talk about the input bias voltages. For the signal amplitudes, your max swing at output is 1Vpeak (if you have single ended output). Divide that by your gain and you get the input differential signal amplitude. What you have to realize is that all opamps work with some kind of feedback. That feedback will try to keep the two inputs very close to each other - "virtual ground". And the feed back will in general define your input CM voltage.

 

[denismos]

Thx to all for your suggestions. My problem still relies in the parallel diff. amp. (avoiding folded version). Actually trying to figure out how this is working, not finding much on the p.diff amp. Keep trying tho. If someone has some tuts on that, i would be grateful. Thx again.

 

[jimito13]

Can you pose a more special and specific question?From your above post little things i can extract for your misunderstanding...

 

[denismos]

Im sorry, I do not know how the parallel diff pair can achieve common input from 0.5 to 2.5 volt, since for me the problem of Vt<Vin,min(0.5V) still remains. I tried to find information about the parallel configuration and how its works but found only these :
In Bakers book p.736
**broken link removed**
and some others articles about rail to rail - wide swing amplifiers etc.. Well in other words nothing that would propel me forward.
So I am asking actually for the theory behind parallel diff amps (how do they provide higher common input voltage?). Hope Im clear now. Thanks again.

 

[poorchava]

I have also seen a definition of small voltage signal being "voltage lower than thermoelectric potential in given enviornment". Under normal conditions it means <26 mV. On the other hand this was a definition used when measuring nonlinear capacitances (like Schottky junction or MOSFET structure)