[180 nm technology TSMC substrate] Well Formation: SSR

[ktx2222]

Dear guys,

I am looking for the information of substrate resistivity of TSMC process. I easily found the resistivity of 65nm/40nm process is 8-12 Ohm-cm.

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However, the well formation of 180nm process is SSR type:

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Does anyone have experience of TSMC technology? Please help me. I would like to know the substrate resistivity of 180nm process. Any instruction will be greatly appreciated.

 

[erikl]

MOSIS differentiates the TSMC processes into EPI and non-EPI ones.
Both use a low-ohmic wafer substrate with a resistivity in the order of 10 Ωcm, which directly forms the substrate for non-EPI circuits. EPI wafers wear a higher-ohmic, several µm thick epitaxial layer with about one to two orders of magnitude higher resistivity on top, which now constitutes the actual substrate resistivity for the circuit, often used for RF- or other circuits which need good substrate isolation between transistors/cells (noise screening).

Due to the additional technological step necessary at the wafer production, EPI wafers cost (a bit) more than their non-EPI counterparts.

I couldn't find out what SSR means for the well formation. Possibly such a well reaches through the total EPI layer thickness down to the low-ohmic wafer substrate (high-voltage retrograde implant), so providing even better isolation between single circuit "islands" embedded in such well rings - a cheaper replacement for SOI tech. circuits.