clock skew and insertion delay target for CTS

[engr]

Hi all,

In clock tree synthesis, how to decide whats the maximum allowable skew and maximum insertion delay for a given clock say k MHZ and also how to decide when we have multiple clocks in the design and whats the relation between these parameters
Thanks in advance

 

[itsmeteja]

skew in general would be around 2 * (inverter delay). maximum allowable skew is less than clock period.


There is no relation b/w insertion delay and clock frequency, but for a subchip it is derived from the top level specification, ideally it is kept as small as possible considering the effects of jitter and dynamic power consumption.

 

[engr]

Thanks itsmeteja
is there any relation between clock skew and insertion delay?
can someone provide more info on these parameters or provide doc if any.
how can i target these two parameters for my design/?
could you pleae give more exlaning on this

 

[itsmeteja]

Only one relation b/w these two is skew is always less than the insertion delay

There is no relation b/w these two parameters, even though if you have 2-10ns of insertion delay you can close the design with less than 0 ps skew ideally.In general try to minimize the insertion delay as much as possible, even you can make lesser ins delay than the target given by top level.You can just add in the top level in that case.

But always try to minimize insertion delay in order to lessen the effects of jitter.

You need to minimize the skew, not to run to setup/hold issue. If you do not meet timing either you can skew or deskew for some flops, so in that case your skew is more than your target skew for those flops. But based on my experience do not skew or deskew blindly in order to meet timing.

 

[raju3295]

quality of CTS engine depends on how low skew & latency values it is providing while maintaining the level of clock tree structree and hw many buffers its inserting
so generally it is followed to give a 0ps target for both in first iteration and from this iteration reports, set the target for both parameters for next iterations,, but for sure it is not stright fwd tat,, this much of skew/latency target will give good quality CTS.
these both depends on the design size even, so for the same tech node and speed, two designs may have diff values.

i have done some experiments on some ARM cores using SOCE, and found that for those cores. it is better to start with skew target of 10% of clock period. but this number is not a concrete one to be used everywhere

 

[jitendravlsi]

what we give to the tool for CTS:
skew : global skew or local skew or a range like min to max skew?
latency: min latency or max latency or range like min to max latency?

what is the purpose to give these constraints like this?

 

[raju3295]

tool generally tries to minimize the global skew and the max latency.

 

[jitendravlsi]

I know this.


anybody else?

 

[raju3295]

hi jitendravlsi,

I did't get u what u mean by, (anybody else ?)
U know some thing different , then directly u can share with all and start discussions.

 

[jitendravlsi]

I dont know the answer.

but this is not the answer to my question.

or let me put my query in other way:

what is the relation between skew and latency?

why we try to keep latency as min as possible?

for eg : if skew is 0 at latency 500 ps (500ps for both launch flop and capture flop) then why we try to make latency as min as possible like 100 or 200 ps.

if we will try to close the design at 500ps latency then which parameters will get affected. or in other words we can say on which parameters the min and max latency is decided?

 

[raju3295]

there is no absoulte mathematical equation between latency and skew, skew may be more and latency can be less, or can be in reverse., one thing i can,, skew can not be more than max latency.
we need less latency because to avoid the effects like OCV,clock jitter, which will be effecting the launch and capture path differently, i dont have any text book or link to prove this, but this is the though i got, am open to discuss on this, and recieve more comments on this

 

[jitendravlsi]

Dear Raju,

please explain in little detail how the latency and ocv are related?

or

how the OCV will get affect by latency?

 

[iwpia50s]

If by latency you mean insertion delay then OCV has a large impact because the larger the insertion delay the greater the impact on insertion delay of the capture path and thus the greater the impact will be on your setup time. If your insertion delay includes a large portion of common path, then CPPR will help reduce the impact of OCV.

 

[raju3295]

yep,
i agree with iwpia,
there could be large delays in capture path, and may not be with great common path, in this scenario, if u reduce the latency it will help in setup.

 

[arjun1110]

Hi,

With large portion of common path between launch and capature, Can we have any (or huge) latency/Insertion delay? If not, then what are the consequences?

Regards

 

[itsmeteja]

If you have huge latency it does directly impact the number of clock buffers so area impact..Suppose your repeaters are not occupying much area but they are giving more delay then it is okay.
If you are having huge latency which does mean that your clock jitter will increase as it is directly prop to ins delay.

So, having the common path b/w launch and capture will remove the cpp but jitter will add up so better try to minimize the ins delay as much as possible.

 

[smarty63]

Can you explain, how clock jitter will increase as Insertion delay increases?

 

[phoenixpavan]

Hi Smarty,

As insertion delay increase..the gates(buffers/inverters) increase resulting in process variations in the clock path which can effect the jitter

cheers,

 

[jaketomy]

hi smarty, as i understand, the jitter component that we incorporate into the design is taken as a percentage of the insertion delay. hence, if the insertion delay is more, jitter is more. now, the reason for why it is taken as a percentage of insertion delay could be because of what was mentioned above.