RS flip-flop is akin to a logic probe, or memory cell. Of course there's the classic 2-transistor formation. We can also choose to build it from logic gates:
* buffer gate with hysteresis
* AND gate with hysteresis
* two invert-gates cross-coupled with hysteresis
* Schmitt trigger (hysteresis is built-in)
To protect the 3.3v device, drop 12v input signals to a safe level via zener diode (or led, diode string).
View attachment 178863
View attachment 178864
That’s THREE possibilities. And how can I2 be “-12V relative to I2”? Do you mean relative to I1? If so, isn’t that the exact same thing as I1 being +12 relative to I2?View attachment 178875
There are 2 possibilities...
a) I1 & I2 are not connected to anything : no change to output.
b) I1 is connected to +12V relative to I2 (no relation to TTL Gnd or VCC) : Q goes positive.
c) I2 is connected to -12V relative to I2 (no relation to TTF Gnd or VCC) : Q Goes negative...
I could use a pair of complementary opto isolators (with current resistory) and then use the outputs of the opto to be the S/R of a flipflop...
That is probably package as (2 E817 opto, 3-4 current limit resistors, 1/2 of dual flipflop [Now scale up to there to 12-20 channels of this on a board and the package count is quite high....
So is there a "neat design that could drastically reduce this?
Typo....That’s THREE possibilities. And how can I2 be “-12V relative to I2”? Do you mean relative to I1? If so, isn’t that the exact same thing as I1 being +12 relative to I2?
I uploaded a drawing earlier... black box. Two inputs I1 and I2... one output QHi,
it´s all just confusing without a drawing.
Klaus
???I uploaded a drawing earlier
Why, it's as clear as day. There's an I1. And an I2. And a Q. And a very nice rectangle.Hi,
Where is 12V where TTL, where NC....?
I´ll better leave... I don´t like to beg for each detail.
Klaus
Brian, It works Just fine...I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.
What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?
Brian.
Voltages on J1 are not at all related to voltages on the rest of the circuit... could be 115VAC relative riding on them... What is known, is that *if* they are momentarily connected to a source there will be a 12VDC *differential* on them of one polarity or the other. The polarity determines which way the FF latches (see all previous definitions of function).I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.
What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?
Brian.
The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5I don't think that would work. R1 and R2 should be in the individual LED connections to U1 and U2 and one of them needs pins 1 and 2 swapping over. Also 'D' and 'C' on U3A should be tied to a logic level.
If the output voltage is at 3.3V logic level and the R/S inputs are tied to 1.5V there is a risk of false flipping.
What are the actual voltages on J1 measured to GND1 ?
Does J1 have to be isolated from the output stage?
Brian
No, the whole purpose of the circuit is that when there is a differential to latch the direction of the differential, and maintain that state when the connections are terminated..there is no difference or there is one.
Vcc is 5VDC so the HC is fine. Yes, pins should be tied... but none of that has anything to do with what I am asking.... Are there components I have not considered which would reduce the component count. For example, multiple opto couplers that are internally configured or have built in latches...finding a lower component, lower cost, smaller solution to my already working circuit was the reason I posted at all....The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5
Vcc is 5VDC so the HC is fine. Yes, pins should be tied... but none of that has anything to do with what I am asking.... Are there components I have not considered which would reduce the component count. For example, multiple opto couplers that are internally configured or have built in latches...finding a lower component, lower cost, smaller solution to my already working circuit was the reason I posted at all....The circuit should work just fine as shown. Except 74HC logic is specified only down to 2v, not 1.5
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