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110 nm layout technology

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kvidhya

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in 110 nm while running layout drc it is giving as


" N _ WELL WITH DIFFERENT POTENTIAL MUST BE SPRERATTED BY A DIFFERENT DNW_LV_MARK"


I AM USING 6V P_cells IT IS GIVING AT ONLY GAURD RINGS
HOW CAN I SOLVE THIS PROBLEM
 

erikl

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Not knowing your technology nor your DRC rules, I 'd assume:

You have N_WELLs WITH DIFFERENT POTENTIAL in your layout. Seems - in your technology - that N-Wells have to be marked (e.g.) by a DNW_LV_MARK marking layer. But there must be different DNW_LV_MARK marking layer polygons for N_WELLs WITH DIFFERENT POTENTIAL. And these have to be separated by a distance corresponding to the DRC rules.
 

kvidhya

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ok what u said is right
but error is showing due to bjt's to all n_wells where bjt's are not in different potential
 

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