10ns CPLD and 133MHz bus

[buenos]

How can work a CPLD based peripheral, connected to a 133MHz DSP external bus in a PCB?

How can access the DSP to this? only with a lot of wait cycles?

What is the relationship between the max 300MHz clock frequency, and an internal 6ns delay (-6 speed grade)? What can it do in 256MHz with that 6ns internal delay? I think it is a contradiction.

If I design a 5 stage synchronous combinatorial logic, does it need 6ns/stage to create the output?

 

[buenos]

Did I ask some stupid thing?

 

[Hero]

You need to give some additional explanations.

Period for 133MHz bus is 7.5ns. Setup and hold time in CPLD registers need to be less than this time.

Maximal frequency of CPLD depends on critical path in your design so check CPLD report and choose appropriated speed grade to minimize delay on critical path.

 

[buenos]

path delay. ok.
thanx.