10GHz LC VCO(KVCO=1.6GHz/V) does not work under 9.8GHz

[heisshin]

hello

I am graduate student for Marster degree. and I have a question. please give a answer...


I made 10GHz LC VCO in 55nm CMOS technology.

LC VCO has 4 capacitor bank for changing operating frequency. and LC VCO is not AFC, just using n-mos for connect capacitor bank and LC VCO's output.

LC VCO is work from 9.6GHz to 11.2GHz in post simulation(after extraction, ).

When I tested my chip. My chip only work 9.8~10.2GHz. and i only used 1 capacitor bank for 9.8GHz

here is my opinion

1. LC VCO work in 11.2GHz at simulation, and work in 10.2GHz at real word. because parasitic capacitance and mismatch.

2. I don't kow why VCO is not working under 9.8GHz, because capacitor just make delay about charging the charge.

3. so I think if I connect more capacitor bank, then VCO will work under 9.8GHz. But it's not working, just dead(make nothing)

4. LC VCO is working at 9GHz in simulation, If I connect another capacitor(not capacitor bank) with VCO's output, LC VCO


So my question is " Why LC VCO does not work under 9.8GHz, when I connect another capacitor bank. I think capacitor bank is just delay..."

thank you very much about reading my thread.

thank you!!

 

[Inder7]

please help me out with the working of capacitor bank..
i am using capacitor bank that involves the use of an inverter separating two nmos varactors..i don't know how it works..??

 

[BigBoss]

hello

I am graduate student for Marster degree. and I have a question. please give a answer...


I made 10GHz LC VCO in 55nm CMOS technology.

LC VCO has 4 capacitor bank for changing operating frequency. and LC VCO is not AFC, just using n-mos for connect capacitor bank and LC VCO's output.

LC VCO is work from 9.6GHz to 11.2GHz in post simulation(after extraction, ).

When I tested my chip. My chip only work 9.8~10.2GHz. and i only used 1 capacitor bank for 9.8GHz

here is my opinion

1. LC VCO work in 11.2GHz at simulation, and work in 10.2GHz at real word. because parasitic capacitance and mismatch.

2. I don't kow why VCO is not working under 9.8GHz, because capacitor just make delay about charging the charge.

3. so I think if I connect more capacitor bank, then VCO will work under 9.8GHz. But it's not working, just dead(make nothing)

4. LC VCO is working at 9GHz in simulation, If I connect another capacitor(not capacitor bank) with VCO's output, LC VCO


So my question is " Why LC VCO does not work under 9.8GHz, when I connect another capacitor bank. I think capacitor bank is just delay..."

thank you very much about reading my thread.

thank you!!View attachment 99779

The capacitor bank does not create a delay only, it adds extra capacitors to tank circuit and active part of the VCO, so it's not possible to consider them delay generation source only.
The oscillation condition is well known, while absolute real part of active portion is greter than equivalent real part of others, imaginary part must create a 0 degree phase shift in the loop to maintain the oscillation.
In additional to, have you ever do a Monte Carlo simulation on oscillation frequency ?? I'm sure you'll be surprised because process variations are very effective on oscillator functionality.%20-50 process variations change too much the osc. frequency sometimes it stops the oscillator as in yoru case..

 

[D.A.(Tony)Stewart]

What are the values of your passive parts and values for SRF and Q ? When C increases the Zo reduces with f. when using diodes reverse biased as varicaps, the voltage can get near 0.

I assume the varicaps are a pair of diodes reverse biased with V vs C controlled on one side but if the other side has a large AC swing it can cause forward conduction as V reduces to lower frequency. This drastically lowers the Q of the resonant circuit enough to cause failure for the Barkhausen Criteria for oscillation for your loop gain.

The varicaps may need to be coupled into the circuit so that AC swing does not cause conduction such as a larger DC reverse bias voltage which reduces capacitance so larger diodes are need to maintain the same capacitance to have more pulling range.

Naturally standing waves, supply decoupling and signal controlled impedances are also factors in the layout.

Can you share more details on everything?

 

[Inder7]

how to simulate an nmos varactor in accumulation mode in cadence?how to check to mode of operation?is any inbuily symbol available for it or we have to simulate it using nmos transistor only?

 

[BigBoss]

Have you ever considered MC simulations ?? There may be huge process variations with 55nm tech.
Let me give you an example..
I builded up a VCO that works 6.8GHz using with 0.25 BiCMOS process years ago, and MC simulations showed me that there is %25 divergence from standard post simulation results..
Especially Varicaps,shotest length MOSs may be very sensitive to process variables.
I think this difference is coming from process variations.