deepameta1919
Newbie level 1
Can anybody tell the self synchronizer implementation in 10GBASE-R PCS?
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Can anybody tell the self synchronizer implementation in 10GBASE-R PCS?
/* This temp stuff is used to parallelize IEEE802.3 clause 49 scrambler and descrambler */
/* - k=0 denotes the first bit to send, k=(COVERAGE*BUSWIDTH-1) is the last */
/* - n=0 denotes the bit0 bit to send in a word, BUSWIDTH-1 is the last */
/* - o=0 denotes the word0 to send, COVERAGE-1 denotes the word N */
#include <stdio.h>
#include <string.h>
/**/
#define BUSWIDTH 32 /* Parallel bus width */
#define COVERAGE 2 /* #*BUSWIDTH cover states */
#define PLEN 59 /* of the length of poly */
/* local functions */
static inline int k2n( int k )
{
return (k%BUSWIDTH); /* Here is the bit position within a WORD */
}
static inline int k2o( int k )
{
return (k/BUSWIDTH); /* Here is the word number in sequence */
}
/* The generator polynomial: */
int G[PLEN];
main()
{
int i,j,k,m,n,o;
/* Initialize the generator polynomial G(x) = 1+x^39+x^58 */
memset( G, 0, sizeof(G) );
G[39] = 1;
G[58] = 1;
/**/
/* Run through COVERAGE*BUSWIDTH bits that can keep track on S states */
for( j=COVERAGE; j<2*COVERAGE; j++ )
for( i=0; i<BUSWIDTH; i++ )
{
k = j*BUSWIDTH+i; /* Here is the bit number to deal with */
n = k2n(k); /* Here is the bit position within a WORD */
o = k2o(k); /* Here is the word number in sequence */
printf( "b%.3i: O%i(%i) <= I%i(%i) ", k, o, n, o, n );
for( m=0; m< PLEN; m++ ) if( G[m] ) printf( "XOR O%i(%i) ", k2o(k-m), k2n(k-m));
printf( ";\n" );
}
}
/* This temp stuff is used to parallelize IEEE802.3 clause 49 scrambler and descrambler */
/* - k=0 denotes the first bit received, k=(COVERAGE*BUSWIDTH-1) is the last */
/* - n=0 denotes the bit0 bit received a word, BUSWIDTH-1 is the last */
/* - o=0 denotes the word0 received, COVERAGE-1 denotes the word N */
#include <stdio.h>
#include <string.h>
/**/
#define BUSWIDTH 32 /* Parallel bus width */
#define COVERAGE 2 /* #*BUSWIDTH cover states */
#define PLEN 59 /* of the length of poly */
/* local functions */
static inline int k2n( int k )
{
return (k%BUSWIDTH); /* Here is the bit position within a WORD */
}
static inline int k2o( int k )
{
return (k/BUSWIDTH); /* Here is the word number in sequence */
}
/* The generator polynomial: */
int G[PLEN+1];
main()
{
int i,j,k,m,n,o;
/* Initialize the generator polynomial G(x) = 1+x^39+x^58 */
memset( G, 0, sizeof(G) );
G[39] = 1;
G[58] = 1;
/**/
/* Run through COVERAGE*BUSWIDTH bits that can keep track on S states */
for( j=COVERAGE; j<2*COVERAGE; j++ )
for( i=0; i<BUSWIDTH; i++ )
{
k = j*BUSWIDTH+i; /* Here is the bit number to deal with */
n = k2n(k); /* Here is the bit position within a WORD */
o = k2o(k); /* Here is the word number in sequence */
printf( "b%.3i: O%i(%i) <= I%i(%i) ", k, o, n, o, n );
for( m=0; m<PLEN; m++ ) if( G[m] ) printf( "XOR I%i(%i) ", k2o(k-m), k2n(k-m));
printf( ";\n" );
}
}
--
-- Implementations:
-- ~~~~~~~~~~~~~~~~~~~~~~~
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--
entity xgbe_SCRAMBLER is
--~~~~~~~~~~~~~~~~~~~~~~~~~~
port
(
-- User Interface
UNSCRAMBLED_DATA_IN : in std_logic_vector(31 downto 0);
DATA_VALID_IN : in std_logic;
SCRAMBLED_DATA_OUT : out std_logic_vector(31 downto 0);
DATA_VALID_OUT : out std_logic;
-- System Interface
USER_CLK : in std_logic;
SYSTEM_RESET : in std_logic
);
end xgbe_SCRAMBLER;
--
architecture RTL of xgbe_SCRAMBLER is
--
signal I0 : std_logic_vector(31 downto 0);
signal O0 : std_logic_vector(31 downto 0);
signal OP : std_logic_vector(31 downto 0);
--
begin
-- Take bits from fabric
MeshIn: for I in 0 to 7 generate
I0( I ) <= UNSCRAMBLED_DATA_IN( 24+I );
I0( I+8 ) <= UNSCRAMBLED_DATA_IN( 16+I );
I0( I+16 ) <= UNSCRAMBLED_DATA_IN( 8+I );
I0( I+24 ) <= UNSCRAMBLED_DATA_IN( I );
end generate;
--
-- As per IEEE 802.3 Fig. 49-8 in Clause 49.
scramblerp: process( USER_CLK )
--
begin
if(USER_CLK'event and USER_CLK = '1') then
if (SYSTEM_RESET = '1') then
O0 <= (others => '0');
DATA_VALID_OUT <= '0';
elsif (DATA_VALID_IN = '1') then
O0( 6 downto 0 ) <= I0( 6 downto 0 ) XOR OP( 31 downto 25 ) XOR OP( 12 downto 6 );
O0( 25 downto 7 ) <= I0( 25 downto 7 ) XOR O0( 18 downto 0 ) XOR OP( 31 downto 13 );
O0( 31 downto 26 ) <= I0( 31 downto 26 ) XOR O0( 24 downto 19 ) XOR O0( 5 downto 0 );
OP <= O0;
DATA_VALID_OUT <= '1';
else
DATA_VALID_OUT <= '0';
end if;
end if;
end process;
--
-- Render bits to transmission order
MeshOu: for I in 0 to 7 generate
SCRAMBLED_DATA_OUT( I ) <= O0( 31-I );
SCRAMBLED_DATA_OUT( I+8 ) <= O0( 31-I-8 );
SCRAMBLED_DATA_OUT( I+16 ) <= O0( 31-I-16 );
SCRAMBLED_DATA_OUT( I+24 ) <= O0( 31-I-24 );
end generate;
--
end RTL;
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--
entity xgbe_DESCRAMBLER is
--~~~~~~~~~~~~~~~~~~~~~~~~~~
port
(
-- User Interface
SCRAMBLED_DATA_IN : in std_logic_vector(31 downto 0);
DATA_VALID_IN : in std_logic;
UNSCRAMBLED_DATA_OUT : out std_logic_vector(31 downto 0);
DATA_VALID_OUT : out std_logic;
-- System Interface
USER_CLK : in std_logic;
SYSTEM_RESET : in std_logic
);
end xgbe_DESCRAMBLER;
--
architecture RTL of xgbe_DESCRAMBLER is
--
signal O0: std_logic_vector(31 downto 0);
signal I0: std_logic_vector(31 downto 0);
signal I1: std_logic_vector(31 downto 0);
signal I2: std_logic_vector(31 downto 0);
--
begin
-- Restore bits transmission order
MeshIn: for I in 0 to 7 generate
I0( I ) <= SCRAMBLED_DATA_IN( 31-I );
I0( I+8 ) <= SCRAMBLED_DATA_IN( 31-I-8 );
I0( I+16 ) <= SCRAMBLED_DATA_IN( 31-I-16 );
I0( I+24 ) <= SCRAMBLED_DATA_IN( 31-I-24 );
end generate;
--
-- As per IEEE 802.3 Fig. 49-10 in Clause 49.
descramblp: process( USER_CLK )
--
begin
--
if(USER_CLK'event and USER_CLK = '1') then
if (SYSTEM_RESET = '1') then
O0 <= (others => '0');
DATA_VALID_OUT <= '0';
elsif (DATA_VALID_IN = '1') then
O0( 6 downto 0 ) <= I0( 6 downto 0 ) XOR I2( 31 downto 25 ) XOR I2( 12 downto 6 );
O0( 25 downto 7 ) <= I0( 25 downto 7 ) XOR I1( 18 downto 0 ) XOR I2( 31 downto 13 );
O0( 31 downto 26 ) <= I0( 31 downto 26 ) XOR I1( 24 downto 19 ) XOR I1( 5 downto 0 );
I1 <= I0;
I2 <= I1;
DATA_VALID_OUT <= '1';
else
DATA_VALID_OUT <= '0';
end if;
end if;
--
end process;
--
-- Render bits from transmission order back to the fabric
MeshOu: for I in 0 to 7 generate
UNSCRAMBLED_DATA_OUT( I ) <= O0( 24+I );
UNSCRAMBLED_DATA_OUT( I+8 ) <= O0( 16+I );
UNSCRAMBLED_DATA_OUT( I+16 ) <= O0( 8+I );
UNSCRAMBLED_DATA_OUT( I+24 ) <= O0( I );
end generate;
--
end RTL;