100G PLL Design in Cadence

[astroshey]

I am running into a very weird issue when calculating the phase noise of my PLL in cadence. The bandwidth of my filter is too large, even though I am calculating the loop filter parameters (Cp Rp C2) using zeta and natural frequency formulas from Razavi's book. Please see the attached image. Can someone suggest any ideas to resolve or troubleshoot this issue. Also, attaching the block diagram of my PLL for reference. Thank you for any help!!

 

[dick_freebird]

There can be PN contributors which are not removed by the filter.

A method of substituting ideal blocks for various sections, or conversely substituting in transistor-level blocks one by one to a full-up behavioral lineup, is how I like to poke at misbehaviors.

 

[astroshey]

I found the ideal freq divider block in rflib. I need to assign the parameters in the block now. My input frequency is around 100GHz, and I need an output frequency of 100MHz - so I need a divide ratio of 1000. I have attached a screenshot of the parameters I have assigned. These parameters are not correct since I am getting a 0 output out of the freq div block (see attached waveform). Please let me know how I should assign the parameters in the freq divider given my frequency requirements. I appreciate any help! Green is the output of my VCO and purple is the output of freq divider.