10-Bit Counter in Altera DE1 using Verilog

[nizdom]

Hi.

I'd like to make a 10-bit Up/Down Counter using Verilog in Altera DE1. It's a decimal counter that counts from 0-1023 with DIR, LOAD and RESET. Reset will get the counter back to 0. DIR will specify if it's going up or down.

I have here a code where it will simply count from 0-15(F). How do you think I can modify it to make it count from 0-1023 and make it an up/down counter?

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
module ex10(CLOCK_50, SW, LEDR, LEDG, PB,
             HEX0, HEX1, HEX2, HEX3);
input CLOCK_50;
input [9:0] SW;
input [3:0] PB;
output [6:0] HEX0, HEX1, HEX2, HEX3;
output [7:0] LEDG;
output [9:0] LEDR;
 
parameter N = 20_000_000;
 
//-------function bcdto7seg ------
function [6:0] bcdto7seg; //(bcd);
input [3:0] bcd;
    
  case (bcd)
  0:  bcdto7seg = 7'b1000000; 
  1:  bcdto7seg = 7'b1111001; 
  2:  bcdto7seg = 7'b0100100; 
  3:  bcdto7seg = 7'b0110000; 
  4:  bcdto7seg = 7'b0011001; 
  5:  bcdto7seg = 7'b0010010; 
  6:  bcdto7seg = 7'b0000010; 
  7:  bcdto7seg = 7'b1111000; 
  8:  bcdto7seg = 7'b0000000; 
  9:  bcdto7seg = 7'b0010000; 
  10: bcdto7seg = 7'b0001000;
  11: bcdto7seg = 7'b0000011;
  12: bcdto7seg = 7'b1000110;
  13: bcdto7seg = 7'b0100001;
  14: bcdto7seg = 7'b0000110;
  15: bcdto7seg = 7'b0001110;
  default:  bcdto7seg = 7'b1111111;                 
 endcase
endfunction
 
assign LEDR = SW;
 
assign HEX0 = bcdto7seg(LEDG[3:0]); //7'b1000000;  //=gfedcba common anode
assign HEX1 = 7'b1111001;  //1
assign HEX2 = 7'b0100100;  //2
assign HEX3 = 7'b0110000;  //3
 
wire [25:0] q;
mycnter #26 cntXXM(CLOCK_50, PB[0], q, 1, N);
 
reg [7:0] LEDG;
initial LEDG =8'b00000000;
always @(posedge CLOCK_50)
   if (q == N) LEDG <= LEDG + 1;
    
endmodule

---

 

[FvM]

How do you think I can modify it to make it count from 0-1023 and make it an up/down counter?

Not at all. The actual counter code is in module cntXXM, not shown in your post. The posted code is unrelated to your question.

Google gives pretty much hits for "Verilog up-down counter", I believe examples can be found also in many Verilog text books.

 

[andre_luis]

Moreover, the code perhaps would not run at the target board DE1, as requested.
Seems as part of some testbench:

[B]initial [/B]LEDG =8'b00000000;

 

[nizdom]

Not at all. The actual counter code is in module cntXXM, not shown in your post. The posted code is unrelated to your question.

Google gives pretty much hits for "Verilog up-down counter", I believe examples can be found also in many Verilog text books.

My bad. Here is the code for the mycnter.

module mycnter(clk, rstn, q, start, stop);
parameter N = 4;  
input clk, rstn;
input [N-1:0] start, stop;
output [N-1:0] q;

reg [N-1:0] q;
initial q = start;
always @(posedge clk)
  if (!rstn) q <= start;
  else  
    begin
      if (q == stop) q <= start;
      else           q <= q + 1;
    end 
  
endmodule

 

[ads-ee]

Change the following line

parameter N = 4;

to

parameter N = 10;

But this counter code does not implement an up/down counter.

- - - Updated - - -

I also don't get your instantiation of the counter:

wire [25:0] q;
mycnter #26 cntXXM(CLOCK_50, PB[0], q, 1, N);

1) what is the #26 supposed to do here? Is it there to cause a syntax error?
2) Don't use positional port association, ONLY use NAMED association of ports (look it up if you don't know)
3) Why the heck is q 26-bits wide? You said you wanted to have a 10-bit counter and the code you were using was a 4-bit counter?
4) I think you need to read a Verilog tutorial.

 

[nizdom]

The counter I posted is a counter that counts from 0-15(f).

Below is the code I made that is a 10-bit counter utilizing the LEDR of the Altera DE1 and showing the count at the 7 segment display. Also, I only need an up counter and not an up/down counter (sorry for that).

In the code below, I wanted to count only from 0-9 and not 0-15(F) but when I omitted the 10-15 from the function bcdto7seg in the code, the output in the 7 segment display, after the count of 9 will show nothing and after like 6 seconds, it counts from 0 again. What shall I do to make it count back to 0 immediately after 9? (mycnter is the same mycnter code I posted above)

Code is here:

module ex10(CLOCK_50, LEDR, PB,
             HEX0, HEX1, HEX2, HEX3);
input CLOCK_50;
input [3:0] PB;
output [6:0] HEX0, HEX1, HEX2, HEX3;
output [9:0] LEDR;

parameter N = 20_000_000;


//-------function bcdto7seg ------
function [6:0] bcdto7seg; //(bcd);
input [3:0] bcd;
	
  case (bcd)
  0:  bcdto7seg = 7'b1000000; 
  1:  bcdto7seg = 7'b1111001; 
  2:  bcdto7seg = 7'b0100100; 
  3:  bcdto7seg = 7'b0110000; 
  4:  bcdto7seg = 7'b0011001; 
  5:  bcdto7seg = 7'b0010010; 
  6:  bcdto7seg = 7'b0000010; 
  7:  bcdto7seg = 7'b1111000; 
  8:  bcdto7seg = 7'b0000000; 
  9:  bcdto7seg = 7'b0010000; 
  default:  bcdto7seg = 7'b0111111;  				
 endcase
endfunction


assign HEX0 = bcdto7seg(LEDR[3:0]); //7'b1000000;  //=gfedcba common anode
assign HEX1 = bcdto7seg(LEDR[7:4]);  //1
assign HEX2 = bcdto7seg(LEDR[9:8]);  //2
assign HEX3 = 7'b0110000;  //3

wire [25:0] q;
mycnter #26 cntXXM(CLOCK_50, PB[0], q, 1, N);

reg [9:0] LEDR;

initial LEDR =8'b00000000;
always @(posedge CLOCK_50)	
if (q == N) LEDR <= LEDR + 1;
	

endmodule

 

[andre_luis]

the output in the 7 segment display, after the count of 9 will show nothing and after like 6 seconds, it counts from 0 again

The code above put the actual value of each nibble of LEDR at the display, coded to 7 seg. You should add an intermediate function to split the variable in separated decimal digits, something like hextobcd.