1 to 8 Demux, Help Plz

[tetooo]

Hi all,
I am tried to write VHDL code for 1 to 8 Demux and that's what i finish with it


LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY Dmux1to8 IS
PORT ( X : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(0 TO 2);
En : IN STD_LOGIC;
W : OUT STD_LOGIC_VECTOR(0 TO 7));
END Dmux1to2;
ARCHITECTURE Structure OF Dmux1to8 IS
SIGNAL m : STD_LOGIC_VECTOR(0 TO 5);
BEGIN
G1: FOR i IN 0 TO 1 GENERATE
Dec_ri: Demux1to2 PORT MAP ( m(i), S(0), X);
G2: FOR i IN 2 TO 5 GENERATE
Dec_left: Demux1to2 PORT MAP ( m(i), S(1));
END GENERATE ;
END GENERATE ;
Demux5: Demux1 to 8 PORT MAP ( m(2),m(3),m(4),m(5), S(2), W(0 TO
7) );
END Structure;


can any one told me if is it right or not?
if there are any mistakes can you help me to correct it ?

 

[TrickyDicky]

its not going to work, because

1. you havent included any libraries for the demuxes to be taken from.
2. Without the library, there is no component declarations.
3. In demux 5, you cannot have spaces in the name.

I have no idea if its going to work even when the above are fixed, becaise you havent included the code for the demuxes.

Why didnt you try and run it throguh a compiler instead of just pasting code in a post?