0 CLK pins and 3 NON_CLK failed to route using a CLK template problem

arash rezaee · Sep 2, 2012

Hi every one.
I have one block which is I2S transmitter. When I attach CLK to this block I have this warning from place and route. I am using ISE 13.3 and working with spartan XC3S50. I don`t know how to fix this warning. I also attached my I2S block VHDL file. I really appreciate for your help.

alexan_e · Sep 2, 2012

I think the problem is in this part

Code:

process(SCK)
variable count : integer range 0 to 63 :=0;
begin
		
		
		[COLOR="#FF0000"]if (count = 0) then
			I2SBUF(62 downto 39) <= INPL(23 downto 0);
			I2SBUF(30 downto 7) <= INPR(23 downto 0);
		end if;[/COLOR]
		
	if falling_edge(SCK) then
	
		if (63-count) > 31 then
			LR <= '0';
		elsif (63-count) <= 31 then
			LR <= '1';
		end if;
		SD(0) <= I2SBUF(63-count);
		count := count + 1;

	end if;

end process;

You should place that part inside the clock

arash rezaee · Sep 2, 2012

I did it but I have the problem again. Also the warning came up in mapping. here is both warning:

LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
symbol "physical_group_SCK/XLXI_1/I_Q1/Q_DUMMY_BUFG" (output signal=SCK) has
a mix of clock and non-clock loads. The non-clock loads are:
Pin I2 of XLXI_1/I_Q3/I_36_32
Pin I1 of XLXI_1/I_Q2/I_36_32
Phase 9 : 0 unrouted; WARNING:Route:455 - CLK Net:XLXN_713 may have excessive skew because
WARNING:Route:455 - CLK Net:SCK may have excessive skew because

0 CLK pins and 3 NON_CLK failed to route using a CLK template problem

arash rezaee

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alexan_e

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arash rezaee

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0 CLK pins and 3 NON_CLK failed to route using a CLK template problem

arash rezaee

Member level 5

Attachments

alexan_e

Administrator

arash rezaee

Member level 5

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