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If the circuit is so complex that there are number of MOS transistors on a board, if we are using 0.8micron process is it that each trasistor will be having the same gate length?
what about resistor and capacitors in this case?
how are they realized?
I'm not familiar with a hybrid circuit you are referring to , but I think the fundamental idea is the same as a monolithic circuit. MOST of the transistors are of the same gate length, with some exception where you sometimes need a weak transistor which is constructed with a longer channel length(for example, the feedback inverter in the latch/flop).
You can put it this way.. the gate length suggested by the technology is the minimum gate length that can be achieved by that technology and engineers want to get the best performance out of it, so that majority of the transistors being used is of the same minimum size.
Transistors are often wide but short length to get high gm. So short length is the limiting factor - hence gate length being the critical dimension quoted. It is more strictly minimum "feature size" which may be slightly different from gate length (and could be different from PMOS to NMOS).
Passives are often larger than minimum feature size because they are not made in the same way as the gate of a MOSFET. For a resistor you might want to use a narrow width to keep length down (and hence area) but design rules don't allow it. Also, tolerances and matching would be poor with very narrow widths. For capacitors you are unlikely to use minimum widths - you need a large area to get even a small capacitor.
If i have a ic (which has several transistors embedded) which says that it uses 0.8micron technology, is it that the lowest possible gate length is 0.8 micron and there can be other transistors with other gate lenghts also?
How are resistors and capacitors realized?
Is micron specification anyway related to the radiation wavelength used for etching process of a substrate?
Yes, there will most likely be transistors with a gate length greater than 0.8um in a 0.8um chip.
Resistors can be done in a number of ways. Most diffusions and polysilicon have a resistance which can be useful depending on the design requirements. Some have a strong voltage dependency and some have a poor tolerance. Temperature coefficients are different. The resistivity is different. Minimum widths are likely to be wider than the minimum feature size.
Capacitors can use gate poly if you want one side to be VSS. They can be poly-poly or poly-metal or metal-metal. The differences can be the quality of the capacitor, the stray capacitance to substrate and the capacitance per unit area (so affecting how large it needs to be). You can also make sandwich capacitors using more than two metal layers.
I have read somewhere that optical lithography is a technology for etching a die. The wavelength of this optical wave is mentioned as nm technology. For example a celeron processor which has 40nm technology uses 40nm wavelength light.
In this case 40nm is the wavelength of light, is it also the gate length?
The lithography is not something I know much about, although I do know the wavelength of the light and the feature size are not the same. It is difficult to make small feature sizes with long wavelengths though. Have a read of these:
Going through the above article gave me an idea that if we wanted to realize 40nm technology using optical lithography as etching process, the light must be of that wavelength.
As UV extends over 10nm-400nm, the technology can go upto 10nm or 0.01um....
What i was able to understand from this is optical wavelength forms a part of technology, without which etching can't be done.
So, optical lithography and phase shift mask lithography are the two techniques we came to know here....
Do anybody know other techniques used for layout technology...
The lithography process for 0.8um almost certainly uses UV wavelength of 365nm. The optical wavelength is used to pattern a photoresist masking layer between 1.0um and 3.0um thick on the surface of the wafer. This resist is patterned then developed using a weak alkali to leave the photoresist in the pattern of the mask. Photoresist is normally positive resist. This resist is resistant to the etches that are used to make the final patterns on the wafer. They are typically novolak resins that can withstand wet acids, alkalis and plasmas. They are removed using either Sulphuric acid doped with hydrogen peroxide which will strip off any organic material, or using an oxygen plasma (creatining ozone radicals which will strip off organic materials).
For 0.35um and smaller, the wavelenth of the UV light was pushed lower for higher resolution (Deep UV) then for 0.1um and smaller pushed even lower into the 195nm range. So using various optical tricks, 195nm can produces features of 65nm. One trick is to pattern the minimum dimension possible with the light source (say 90nm) then lightly etch away the resist in an oxygen plasma. So if you deposit 1.2um of resist and pattern it to produce a cross section of 1200x90nm, then etch away 0.2um of resist in a plamsa, you get 1000x70nm producing a minimum linewidth of 0.07um.
The plasma etch systems are set up to reproduce the photoresist linewidth into whatever material you are etching, so the minimum linewidth is dominated by the photoresist pattern just prior to etching.
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